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"A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy."

Kun Ao et al. (2014)

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DOI: 10.1109/ISICIR.2014.7029486

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-09

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  dblp key:
  - conf/isicir/AoHLWL14
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  - https://dblp.org/rec/conf/isicir/AoHLWL14
Kun Ao, Yajuan He, Liang Li, Yuxin Wang, Qiang Li:
A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy. ISIC 2014: 83-86

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