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Xiaoxiao Liu 0001
Person information
- affiliation: AMD Inc., Santa Clara, CA, USA
- affiliation (PhD 2017): University of Pittsburgh, PA, USA
Other persons with the same name
- Xiaoxiao Liu (aka: Xiao-Xiao Liu, Liu Xiaoxiao) — disambiguation page
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2020 – today
- 2021
- [j4]Xiaoxiao Liu
, Mengjie Mao
Exploring Applications of STT-RAM in GPU Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 238-249 (2021)
2010 – 2019
- 2019
- [j3]Bing Li
Thread Batching for High-performance Energy-efficient GPU Memory Design. ACM J. Emerg. Technol. Comput. Syst. 15(4): 39:1-39:21 (2019) - [i1]Bing Li, Mengjie Mao, Xiaoxiao Liu, Tao Liu, Zihao Liu, Wujie Wen, Yiran Chen, Hai Helen Li:
Thread Batching for High-performance Energy-efficient GPU Memory Design. CoRR abs/1906.05922 (2019) - 2018
- [j2]Yiran Chen, Hai (Helen) Li, Chunpeng Wu, Chang Song, Sicheng Li, Chuhan Min, Hsin-Pai Cheng, Wei Wen, Xiaoxiao Liu
Neuromorphic computing's yesterday, today, and tomorrow - an evolutional view. Integr. 61: 49-61 (2018) - [c11]Xiaoxiao Liu, Wei Wen, Xuehai Qian, Hai Li, Yiran Chen:
Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems. ASP-DAC 2018: 141-146 - 2016
- [j1]Xiaoxiao Liu
Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(5): 617-628 (2016) - [c10]Mengjie Mao, Wujie Wen, Xiaoxiao Liu
TEMP: thread batch enabled memory partitioning for GPU. DAC 2016: 65:1-65:6 - [c9]Sicheng Li, Xiaoxiao Liu
Heterogeneous systems with reconfigurable neuromorphic computing accelerators. ISCAS 2016: 125-128 - 2015
- [c8]Xiaoxiao Liu
An efficient STT-RAM-based register file in GPU architectures. ASP-DAC 2015: 490-495 - [c7]Xiaoxiao Liu
RENO: a high-efficient reconfigurable neuromorphic computing accelerator design. DAC 2015: 66:1-66:6 - [c6]Hai Li
The applications of memristor devices in next-generation cortical processor designs. ISCAS 2015: 17-20 - [c5]Beiye Liu, Xiaoxiao Liu
Hardware acceleration for neuromorphic computing: An evolving view. NVMTS 2015: 1-4 - 2014
- [c4]Xiaoxiao Liu
STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. ASP-DAC 2014: 355-360 - [c3]Xiaoxiao Liu
A heterogeneous computing system with memristor-based neuromorphic accelerators. HPEC 2014: 1-6 - [c2]Hai Li
Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper). ISIC 2014: 124-127 - [c1]Hai Li
Emerging memristor technology enabled next generation cortical processor. SoCC 2014: 377-382
Coauthor Index
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