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Tso-Bing Juang
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2020 – today
- 2023
- [c15]Tso-Bing Juang, Chun-Chi Fan, Guan-Zhong Lin:
Lower-Error and Area-Efficient Complex Divider Design using Logarithmic Number Systems (LNS). ISOCC 2023: 185-186
2010 – 2019
- 2019
- [c14]Tso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin:
Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number Systems. ISOCC 2019: 180-181 - 2018
- [c13]Tso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin:
Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems. ISOCC 2018: 170-171 - 2017
- [c12]Tso-Bing Juang, Ying-Ren Lee:
Low-area implementations of concurrent error detection logarithmic processors. ISOCC 2017: 131-132 - 2016
- [c11]Tso-Bing Juang, Ying-Ren Lee, Chin-Chieh Chiu:
Low-cost concurrent error detection schemes for logarithmic converters. ISOCC 2016: 213-214 - [c10]Tso-Bing Juang, Ying-Ren Lee:
Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications. ISVLSI 2016: 625-630 - 2014
- [c9]Tso-Bing Juang, Yu-Ming Chiu:
Fast binary to BCD converters for decimal communications using new recoding circuits. ISIC 2014: 188-191 - 2012
- [j11]Tso-Bing Juang, Chao-Tsung Kuo, Go-Long Wu, Jian-Hao Huang:
Multifunction RNS Modulo 2n ± 1 Multipliers. J. Circuits Syst. Comput. 21(4) (2012) - [c8]Chao-Tsung Kuo, Tso-Bing Juang:
A lower error antilogarithmic converter using novel four-region piecewise-linear approximation. APCCAS 2012: 507-510 - [c7]Tso-Bing Juang, Jian-Hao Huang:
Multifunction RNS modulo (2n±1) multipliers based on modified booth encoding. APCCAS 2012: 515-518 - [c6]Tso-Bing Juang, Hsin-Hao Peng, Han-Lung Kuo:
Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders. ISOCC 2012: 239-242 - 2011
- [c5]Tso-Bing Juang, Hsin-Hao Peng, Chao-Tsung Kuo:
Area-efficient 3-input decimal adders using simplified carry and sum vectors. VLSI-SoC 2011: 25-30 - 2010
- [j10]Tso-Bing Juang, Chin-Chieh Chiu, Ming-Yu Tsai:
Improved Area-Efficient Weighted Modulo 2n + 1 Adder Design With Simple Correction Schemes. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 198-202 (2010) - [c4]Tso-Bing Juang, Pramod Kumar Meher, Chung-Chun Kuan:
Area-efficient parallel-prefix Ling adders. APCCAS 2010: 736-739
2000 – 2009
- 2009
- [j9]Tso-Bing Juang, Ming-Yu Tsai, Chin-Chieh Chiu:
Corrections to "VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection" [Sep 08 897-901]. IEEE Trans. Circuits Syst. II Express Briefs 56-II(3): 260-261 (2009) - [j8]Pramod Kumar Meher, Javier Valls
, Tso-Bing Juang, K. Sridharan, Koushik Maharatna
50 Years of CORDIC: Algorithms, Architectures, and Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1893-1907 (2009) - [j7]Tso-Bing Juang, Sheng-Hung Chen, Huang-Jia Cheng:
A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications. IEEE Trans. Circuits Syst. II Express Briefs 56-II(12): 931-935 (2009) - 2008
- [j6]Tso-Bing Juang:
Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations. IEEE Trans. Circuits Syst. II Express Briefs 55-II(11): 1139-1143 (2008) - [c3]Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li:
A novel VLSI iterative divider architecture for fast quotient generation. ISCAS 2008: 3358-3361 - 2006
- [c2]Tso-Bing Juang:
Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations. APCCAS 2006: 1539-1542 - 2005
- [j5]Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, Jenq-Shiun Jan:
A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition. IEICE Trans. Inf. Syst. 88-D(7): 1464-1471 (2005) - [j4]Tso-Bing Juang, Shen-Fu Hsiao:
Low-error carry-free fixed-width multipliers with low-cost compensation circuits. IEEE Trans. Circuits Syst. II Express Briefs 52-II(6): 299-303 (2005) - [j3]Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang, Cheng-Han Lee:
Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(8): 1568-1579 (2005) - 2004
- [j2]Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang:
A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations. IEEE Signal Process. Lett. 11(2): 152-155 (2004) - [j1]Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai:
Para-CORDIC: parallel CORDIC rotation algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(8): 1515-1524 (2004) - 2002
- [c1]Tso-Bing Juang, Jeng-Hsiun Jan, Ming-Yu Tsai, Shen-Fu Hsiao:
Partition methodology for the final adder in a tree-structure parallel multiplier generator. APCCAS (1) 2002: 471-474
Coauthor Index
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