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Henrik Sjöland
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2020 – today
- 2024
- [j27]Christian Elgaard
, Mustafa Özen
Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS. IEEE J. Solid State Circuits 59(2): 321-336 (2024) - [c57]Rikard Gannedahl, Henrik Sjöland:
Capacitive Cancellation in Compact Integrated Multi-GHz Differential Passive Baseband Filters. NewCAS 2024: 208-212 - 2023
- [c56]Rikard Gannedahl, Javad Bagheri Asli
A Modular System-level Testbench for 6G Beamforming Applications with Near Circuit-Level Fidelity. NEWCAS 2023: 1-5 - [c55]Rikard Gannedahl, Henrik Sjöland
A mm-Wave Differential-to-Quadrature Frequency Tripler with Automatic Locking and Quadrature Correction. NorCAS 2023: 1-6 - 2022
- [c54]Baktash Behmanesh
An 88% fractional bandwidth reconfigurable power amplifier for NB-IoT and LTE-M in 22 nm CMOS FDSOI. NorCAS 2022: 1-4 - [c53]Sidra Muneer, Jesus Rodriguez Sanchez, Liesbet Van der Perre
System Design and Performance for Antenna Reservation in Massive MIMO. VTC Fall 2022: 1-5 - 2021
- [j26]Harsh Tataria
6G Wireless Systems: Vision, Requirements, Challenges, Insights, and Opportunities. Proc. IEEE 109(7): 1166-1199 (2021) - [j25]Muris Sarajlic
Power Scaling Laws for Radio Receiver Front Ends. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 2183-2195 (2021) - [c52]Peng Chen, Stefan Andersson, Sten E. Gunnarsson, Henrik Sjöland
Analysis and Design of an 1-20 GHz Track and Hold Circuit. ISCAS 2021: 1-5 - [c51]Rikard Gannedahl
An LO Frequency Tripler with Phase Shifter and Detector in 28nm FD-SOI CMOS for 28-GHz Transceivers. NorCAS 2021: 1-7 - 2020
- [c50]Sidra Muneer, Liang Liu
Handling PA Nonlinearity in Massive MIMO: What are the Tradeoffs Between System Capacity and Power Consumption. ACSSC 2020: 974-978 - [i2]Harsh Tataria, Mansoor Shafi, Andreas F. Molisch, Mischa Dohler, Henrik Sjöland, Fredrik Tufvesson:
6G Wireless Systems: Vision, Requirements, Challenges, Insights, and Opportunities. CoRR abs/2008.03213 (2020)
2010 – 2019
- 2019
- [j24]Mohammed Abdulaziz
Improving Receiver Close-In Blocker Tolerance by Baseband Gm-C Notch Filtering. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 885-896 (2019) - [c49]Reza Bagger, Henrik Sjöland
An 11 GHz-Bandwidth Variable Gain Ka-Band Power Amplifier for 5G Applications. ESSCIRC 2019: 181-184 - [c48]Yunus Dawji, Fredrik Zetterblom, Sergio Benages, Berta Morral, Siyu Tan, Henrik Sjöland
A 65-nm CMOS Low-Power Front-End for 3rd Generation DNA Sequencing. IEEE SENSORS 2019: 1-4 - [i1]Muris Sarajlic, Liang Liu, Henrik Sjöland, Ove Edfors:
Low Power Receiver Front Ends: Scaling Laws and Applications. CoRR abs/1907.07136 (2019) - 2018
- [j23]Staffan Ek, Tony Påhlsson
A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers. IEEE J. Solid State Circuits 53(7): 1988-2000 (2018) - [c47]Imad ud Din, Stefan Andersson, Therese Forsberg, Henrik Sjöland
A 24GHz, 18dBm, Broadband, Three Stacked Power Amplifier in 28nm FDSOI. NORCAS 2018: 1-4 - [c46]Therese Forsberg, Johan Wernehag, Henrik Sjöland
A 4.3-mW mm-Wave Divide-by-Two Circuit with 30% Locking Range in 28-nm FD-SOI CMOS. NORCAS 2018: 1-4 - 2017
- [j22]Mohammed Abdulaziz
A Linearization Technique for Differential OTAs. IEEE Trans. Circuits Syst. II Express Briefs 64-II(9): 1002-1006 (2017) - [j21]Imad ud Din
Two Tunable Frequency Duplexer Architectures for Cellular Transceivers. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(11): 2988-2999 (2017) - [c45]Staffan Ek, Tony Påhlsson, Anders Carlsson, Andreas Axholt, Anna-Karin Stenman, Henrik Sjöland
A 16-20 GHz LO system with 115 fs jitter for 24-30 GHz 5G in 28 nm FD-SOI CMOS. ESSCIRC 2017: 251-254 - 2016
- [j20]Xiaodong Liu, Anders Nejdel, Mattias Palm, Lars Sundström
A 65 nm CMOS Wideband Radio Receiver With ΔΣ-Based A/D-Converting Channel-Select Filters. IEEE J. Solid State Circuits 51(7): 1566-1578 (2016) - [j19]Rakesh Gangarajaiah, Mohammed Abdulaziz
A Digitally Assisted Nonlinearity Mitigation System for Tunable Channel Select Filters. IEEE Trans. Circuits Syst. II Express Briefs 63-II(1): 69-73 (2016) - [c44]Tobias Tired, Henrik Sjöland
Comparison of two SiGe 2-stage E-band power amplifier architectures. APCCAS 2016: 666-669 - [c43]Johan Wernehag, Waqas Ahmad, Henrik Sjöland
A 30dBm PA for MTC communication in 65nm CMOS technology. LASCAS 2016: 147-150 - 2015
- [j18]Anders Nejdel, Henrik Sjöland
A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching. IEEE J. Solid State Circuits 50(5): 1137-1147 (2015) - [j17]Reza Meraji, S. M. Yasser Sherazi, John B. Anderson, Henrik Sjöland
Low Power Analog and Digital (7, 5) Convolutional Decoders in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1863-1872 (2015) - [c42]Anders Nejdel, Xiaodong Liu, Mattias Palm, Lars Sundström
A 0.6-3.0GHz 65nm CMOS radio receiver with ΔΣ-based A/D-converting channel-select filters. ESSCIRC 2015: 299-302 - [c41]Waqas Ahmad, Mohammed Abdulaziz, Markus Törmänen, Henrik Sjöland
CMOS adaptive TIA with embedded single-ended to differential conversion for analog optical links. ISCAS 2015: 658-661 - [c40]Waqas Ahmad, Leijun Xu, Markus Törmänen, Henrik Sjöland
A fully integrated 26 dBm linearized RF power amplifier in 65nm CMOS technology. ISCAS 2015: 1306-1309 - [c39]Anh Chu, Navneeta Deo, Waqas Ahmad, Markus Törmänen, Henrik Sjöland:
An ultra-low power charge-pump PLL with high temperature stability in 130 nm CMOS. NEWCAS 2015: 1-4 - 2014
- [j16]Carl Bryant, Henrik Sjöland
A 0.55 mW SAW-Less Receiver Front-End for Bluetooth Low Energy Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(3): 262-272 (2014) - [j15]Mohammed Abdulaziz
A Compensation Technique for Two-Stage Differential OTAs. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 594-598 (2014) - [j14]Peter Sjöblom
Constant Mismatch Loss Boundary Circles and Their Application to Optimum State Distribution in Adaptive Matching Networks. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 922-926 (2014) - [c38]Carl Bryant, Henrik Sjöland
A 2.45GHz, 50uW wake-up receiver front-end with -88dBm sensitivity and 250kbps data rate. ESSCIRC 2014: 235-238 - [c37]Mohammed Abdulaziz, Markus Törmänen, Henrik Sjöland
A 4th order Gm-C filter with 10MHz bandwidth and 39dBm IIP3 in 65nm CMOS. ESSCIRC 2014: 367-370 - [c36]Jonas Lindstrand, Ivaylo Vasilev, Henrik Sjöland
A low band cellular terminal antenna impedance tuner in 130nm CMOS-SOI technology. ESSCIRC 2014: 459-462 - [c35]Peter Nilsson, Pietro Andreani, Krzysztof Kuchcinski
Lessons from ten years of the international master's program in System-on-Chip. EWME 2014: 187-192 - [c34]S. M. Yasser Sherazi, Henrik Sjöland
A digital baseband for low power FSK based receiver in 65 nm CMOS. ICECS 2014: 159-162 - [c33]Robabeh Amirkhanzadeh, Henrik Sjöland
L-band 180° passive phase shifter employing auto-transformer in an SOS process. ISCAS 2014: 333-336 - [c32]Therese Forsberg, Henrik Sjöland
A 65 nm CMOS varactorless mm-wave VCO. ISIC 2014: 54-57 - [c31]Tobias Tired, Henrik Sjöland
A 28 GHz SiGe QVCO with an I/Q phase error detector for an 81-86 GHz E-band transceiver. ISIC 2014: 58-61 - [c30]Henrik Sjöland
Ultra low power transceivers for wireless sensors and body area networks. ISMICT 2014: 1-5 - [c29]Waqas Ahmad, Anders Nejdel, Markus Törmänen, Henrik Sjöland
Fully integrated radio over fiber downlink for distributed multi-antenna systems in 65 nm CMOS. NEWCAS 2014: 353-356 - [c28]Tobias Tired, Henrik Sjöland
A 28 GHz SiGe QVCO and divider for an 81-86 GHz E-band beam steering transmitter PLL. NORCHIP 2014: 1-4 - [c27]Rakesh Gangarajaiah, Mohammed Abdulaziz, Liang Liu
Digitally assisted adaptive non-linearity suppression scheme for RF front ends. PIMRC 2014: 623-627 - 2013
- [j13]S. M. Yasser Sherazi, Joachim Neves Rodrigues, Omer Can Akgun
Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain. Microprocess. Microsystems 37(4-5): 494-504 (2013) - [j12]Imad ud Din, Johan Wernehag, Stefan Back Andersson, Sven Mattisson, Henrik Sjöland
Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 60-II(5): 242-246 (2013) - [c26]Anders Nejdel, Markus Törmänen, Henrik Sjöland
A 0.7 - 3.7 GHz six phase receiver front-end with third order harmonic rejection. ESSCIRC 2013: 279-282 - [c25]Waqas Ahmad, Markus Törmänen, Henrik Sjöland
Photodiodes in deep submicron CMOS process for fully integrated optical receivers. ESSDERC 2013: 135-138 - [c24]Waqas Ahmad, Markus Törmänen, Henrik Sjöland
Performance evaluation of N-well/P-sub photodiodes in 65nm CMOS process. ICAIT 2013: 135-136 - [c23]Reza Meraji, John B. Anderson, Henrik Sjöland, Viktor Öwall:
A 3μW 500 kb/s ultra low power analog decoder with digital I/O in 65 nm CMOS. ICECS 2013: 349-352 - [c22]Reza Meraji, S. M. Yasser Sherazi, John B. Anderson, Henrik Sjöland
Analog and digital approaches for an energy efficient low complexity channel decoder. ISCAS 2013: 1564-1567 - [c21]Mohammadreza Pourakbar, Markus Törmänen, Michael Faulkner
An LC-based tunable low-isolation device for adaptive duplexers. NORCHIP 2013: 1-4 - [c20]Tobias Tired, Henrik Sjöland
A 1V SiGe power amplifier for 81-86 GHz E-band. NORCHIP 2013: 1-4 - [c19]Shubo Yan, Mattias Andersson, Henrik Sjöland
A 31.25/125MSps continuous-time ΔΣ ADC with 64/59db SNDR in 130nm CMOS. NORCHIP 2013: 1-4 - 2012
- [j11]Henrik Sjöland
A Receiver Architecture for Devices in Wireless Body Area Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(1): 82-95 (2012) - [c18]S. M. Yasser Sherazi, Peter Nilsson, Henrik Sjöland
A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS. ICECS 2012: 448-451 - 2011
- [j10]Mostafa Savadi Oskooei, Nasser Masoumi, Mahmoud Kamarei, Henrik Sjöland
A CMOS 4.35-mW +22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers. IEEE J. Solid State Circuits 46(6): 1382-1391 (2011) - [c17]Andreas Axholt, Henrik Sjöland
A 2.25mW inductor-less 24 GHz CML frequency divider in 90nm CMOS. ECCTD 2011: 77-80 - [c16]Jonas Lindstrand, Carl Bryant, Markus Törmänen, Henrik Sjöland:
A 1.6-2.6GHz 29dBm injection-locked power amplifier with 64% peak PAE in 65nm CMOS. ESSCIRC 2011: 299-302 - [c15]Carl Bryant, Henrik Sjöland
A 65nm CMOS 282μW 915MHz direct conversion receiver front-end. ESSCIRC 2011: 547-550 - [c14]S. M. Yasser Sherazi, Peter Nilsson, Omer Can Akgun
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. ISCAS 2011: 837-840 - [c13]Reza Meraji, John B. Anderson, Henrik Sjöland
An analog (7, 5) convolutional decoder in 65 nm CMOS for low power wireless applications. ISCAS 2011: 2881-2884 - [c12]Reza Meraji, John B. Anderson, Henrik Sjöland
Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS. NORCHIP 2011: 1-4 - [c11]Anders Nejdel, Markus Törmänen, Henrik Sjöland
A linearized 1.6-5 GHz low noise amplifier using positive feedback in 65 nm CMOS. NORCHIP 2011: 1-4 - [c10]Ying Wu, Xiaodong Liu, Dawei Ye
A 0.13µm CMOS ΔΣ PLL FM transmitter. NORCHIP 2011: 1-4 - 2010
- [c9]Robabeh Amirkhanzadeh, Henrik Sjöland, Ajay Tikka, Mike Faulkner
Comparative analysis of switching performance of transistors in SOS process for RF applications. APCCAS 2010: 1111-1114 - [c8]Andreas Axholt, Henrik Sjöland
A 24-GHz 90-nm CMOS beamforming receiver front-end with analog baseband phase rotation. ESSCIRC 2010: 346-349
2000 – 2009
- 2009
- [j9]Vandana Bassoo, Kevin Tom, Abdul Kader Mustafa, Ellie Cijvat, Henrik Sjöland
A Potential Transmitter Architecture for Future Generation Green Wireless Base Station. EURASIP J. Wirel. Commun. Netw. 2009 (2009) - [j8]Lars Aspemyr, Henrik Sjöland
Third-order nonlinearity vs. load impedance for CMOS low-noise amplifiers. Integr. 42(1): 89-94 (2009) - 2008
- [c7]Johan Wernehag, Henrik Sjöland
60 GHz 130-nm CMOS second harmonic power amplifiers. APCCAS 2008: 300-303 - [c6]Markus Törmänen, Henrik Sjöland
A 25-GHz differential LC-VCO in 90-nm CMOS. APCCAS 2008: 554-557 - [c5]Ellie Cijvat, Henrik Sjöland, Kevin Tom, Mike Faulkner
A comparison of polar transmitter architectures using a GaN HEMT power amplifier. ICECS 2008: 1075-1078 - 2007
- [j7]Peter Sjöblom
Measured CMOS Switched High-Quality Capacitors in a Reconfigurable Matching Network. IEEE Trans. Circuits Syst. II Express Briefs 54-II(10): 858-862 (2007) - 2006
- [c4]Essam Atalla, Emad Hegazi, Henrik Sjöland
An all-digital Sigma-Delta-frequency discriminator of arbitrary order. ISCAS 2006 - 2005
- [j6]Peter Sjöblom
An adaptive impedance tuning CMOS circuit for ISM 2.4-GHz band. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1115-1124 (2005) - [c3]Ellie Cijvat, Niklas Troedsson, Henrik Sjöland
A 2.4 GHz CMOS power amplifier using internal frequency doubling. ISCAS (3) 2005: 2683-2686 - 2003
- [j5]Henrik Sjöland
A merged CMOS LNA and mixer for a WCDMA receiver. IEEE J. Solid State Circuits 38(6): 1045-1050 (2003) - [c2]Ellie Cijvat, Henrik Sjöland
A fully integrated 2.45 GHz 0.25μm CMOS power amplifier. ICECS 2003: 1094-1097 - 2002
- [j4]Pietro Andreani, Henrik Sjöland
Tail current noise suppression in RF CMOS VCOs. IEEE J. Solid State Circuits 37(3): 342-348 (2002) - 2001
- [j3]Emad Hegazi
A filtering technique to lower LC oscillator phase noise. IEEE J. Solid State Circuits 36(12): 1921-1930 (2001) - [c1]Pietro Andreani, Henrik Sjöland
A 2.2 GHz CMOS VCO with inductive degeneration noise suppression. CICC 2001: 197-200
1990 – 1999
- 1998
- [j2]Henrik Sjöland
A 100-MHz CMOS wide-band IF amplifier. IEEE J. Solid State Circuits 33(4): 631-634 (1998) - [j1]Henrik Sjöland
A 160-MHz bipolar wide-band IF amplifier. IEEE J. Solid State Circuits 33(10): 1555-1558 (1998)
Coauthor Index
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last updated on 2024-10-07 22:20 CEST by the dblp team
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