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ICCD 2012: Montreal, QC, Canada
- 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-3051-0
Keynote Papers
- Valentina Salapura:
Cloud computing: Virtualization and resiliency for data center computing. 1-2
30th Anniversary
- Josep Torrellas:
FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper. 3-4 - Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Pratap Pattnaik, Josep Torrellas:
FlexRAM: Toward an advanced Intelligent Memory system. 5-14 - John S. Seng, Dean M. Tullsen
, George Z. N. Cai:
Retrospective on "Power-Sensitive Multithreaded Architecture". 15-16 - John S. Seng, Dean M. Tullsen
Power-sensitive multithreaded architecture. 17-24 - Krishna Kant, Ravishankar K. Iyer, Prasant Mohapatra:
Architectural impact of secure socket layer on Internet servers: A retrospect. 25-26 - Krishna Kant, Ravishankar K. Iyer, Prasant Mohapatra:
Architectural impact of secure socket layer on Internet servers. 27-34 - Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger:
Exploiting microarchitectural redundancy for defect tolerance. 35-42 - Davide Bertozzi, Luca Benini
A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip. 43-44 - Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini
Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs. 45-48
Computer Systems 1
- Sergio Johann Filho, Alexandra Aguiar, Felipe Gohring de Magalhaes, Oliver B. Longhi, Fabiano Hessel
Task model suitable for dynamic load balancing of real-time applications in NoC-based MPSoCs. 49-54 - Pablo Abad Fidalgo
BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip. 55-60
Processor Architecture 1
- Yu Liu, Wei Zhang:
Exploiting multi-level scratchpad memories for time-predictable multicore computing. 61-66 - Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang
SECRET: Selective error correction for refresh energy reduction in DRAMs. 67-74
Electronic Design Automation 1
- Yi Wang, Dan Zhao, Jian Li:
DuSCA: A multi-channeling strategy for doubling communication capacity in wireless NoC. 75-80 - Siyu Yue, Di Zhu, Yanzhi Wang, Massoud Pedram:
Reinforcement learning based dynamic power management with a hybrid power supply. 81-86
Computer Systems 2
- Isaac Liu, Jan Reineke, David Broman, Michael Zimmer, Edward A. Lee
A PRET microarchitecture implementation with repeatable timing and competitive performance. 87-93 - Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrián Cristal
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. 94-101
Processor Architecture 2
- Arun K. Kanuparthi, Ramesh Karri
A high-performance, low-overhead microarchitecture for secure program execution. 102-107 - Mohammad Ghasemazar, Hadi Goudarzi, Massoud Pedram:
Robust optimization of a Chip Multiprocessor's performance under power and thermal constraints. 108-114
Electronic Design Automation 2
- Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao
Hierarchical modeling of Phase Change memory for reliable design. 115-120 - Ying Teng, Baris Taskin:
Clock mesh synthesis method using the Earth Mover's Distance under transformations. 121-126
Special Session Hardware Security
- David Hély
Malicious key emission via hardware Trojan against encryption system. 127-130 - Yier Jin
Exposing vulnerabilities of untrusted computing platforms. 131-134 - David Hély
A physical unclonable function based on setup time violation. 135-138 - Trey Reece
Stealth assessment of hardware Trojans in a microcontroller. 139-142 - Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno:
Design and evaluation of a delay-based FPGA Physically Unclonable Function. 143-146
Text, Verification and Security 1
- Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh:
Adaptable intrusion detection using partial runtime reconfiguration. 147-152 - Subramanian Poothamkurissi Swaminathan, Pey-Chang Kent Lin, Sunil P. Khatri:
Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening. 153-158 - Dibakar Gope, D. M. H. Walker:
Maximizing crosstalk-induced slowdown during path delay test. 159-166
Processor Architecture 3
- Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch:
Embedded way prediction for last-level caches. 167-174 - Dragomir Milojevic
Thermal characterization of cloud workloads on a power-efficient server-on-chip. 175-182 - Mario Donato Marino
RFiop: RF-memory path to address on-package I/O pad and memory controller scalability. 183-188
Electronic Design Automation 3
- Yi-Ling Hsieh, Tsung-Yi Ho
Design methodology for sample preparation on digital microfluidic biochips. 189-194 - Rajeev Kumar, Ayan Mandal, Sunil P. Khatri:
An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT. 195-200 - Can Sitik, Baris Taskin:
Multi-voltage domain clock mesh design. 201-206
Computer Systems 3
- Claus Braun, Stefan Holst, Hans-Joachim Wunderlich, Juan Manuel Castillo-Sanchez, Joachim Gross
Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures. 207-212 - Chengguang Ma, Shun'an Zhong, Hua Dang:
Understanding variance propagation in stochastic computing systems. 213-218
Electronic Design Automation 4
- Morteza Damavandpeyma, Sander Stuijk
Parametric throughput analysis of scenario-aware dataflow graphs. 219-226 - Pavlos M. Mattheakis, Christos P. Sotiriou, Peter A. Beerel:
A polynomial time flow for implementing free-choice Petri-nets. 227-234
Circuit Design 1
- Shinichi Nishizawa, Tohru Ishihara
A flexible structure of standard cell and its optimization method for near-threshold voltage operation. 235-240 - Yoon Seok Yang, Reeshav Kumar, Gwan Choi, Paul Gratz
WaveSync: A low-latency source synchronous bypass network-on-chip architecture. 241-248
Computer Systems 4
- Elena Kakoulli
HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips. 249-255 - Firas Hawi, Mohamad Sawan:
Phase-based passive stereovision systems dedicated to cortical visual stimulators. 256-262 - Zhuo Ruan, David A. Penry:
Interface design for synthesized structural hybrid microarchitectural simulators. 263-270 - Chang-Chih Chen, Fahad Ahmed, Linda Milor
A comparative study of wearout mechanisms in state-of-art microprocessors. 271-276
Processor Architecture 4
- Gregory A. Chadwick, Simon W. Moore
Mamba: A scalable communication centric multi-threaded processor architecture. 277-283 - Tosiron Adegbija, Ann Gordon-Ross, Arslan Munir
Dynamic phase-based tuning for embedded systems using phase distance mapping. 284-290 - Zhen-Hao Zhang, Dong Tong, Xiaoyin Wang, Jiangfang Yi, Keyi Wang:
SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency. 291-296 - Alejandro Valero
Analyzing the optimal ratio of SRAM banks in hybrid caches. 297-302
Circuit Design 2
- Peng Li, Weikang Qian, David J. Lilja:
A stochastic reconfigurable architecture for fault-tolerant computation with sequential logic. 303-308 - Zoran Jaksic
Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs. 309-314 - Armin Alaghi, John P. Hayes:
A spectral transform approach to stochastic circuits. 315-321 - Samy Zaynoun, Muhammed S. Khairy, Ahmed M. Eltawil
Fast error aware model for arithmetic and logic circuits. 322-328
Best Paper Session
- Christos Vezyrtzis, Yannis P. Tsividis, Steven M. Nowick:
Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications. 329-336 - HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding, Onur Mutlu:
Row buffer locality aware caching policies for hybrid memories. 337-344 - Saurabh Kothawade, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Mitigating NBTI in the physical register file through stress prediction. 345-351 - Mehdi Kamal, Qing Xie, Massoud Pedram, Ali Afzali-Kusha, Saeed Safari
An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits. 352-357 - Zhe Zhang, Weijun Xiao, Nohhyun Park, David J. Lilja:
Memory module-level testing and error behaviors for phase change memory. 358-363
Computer Systems 5
- Mohammad Fattah, Marco Ramírez, Masoud Daneshtalab
CoNA: Dynamic application mapping for congestion reduction in many-core systems. 364-370 - Jason H. Gao, Anirudh Sivaraman, Niket Agarwal, HaoQi Li, Li-Shiuan Peh:
DIPLOMA: Consistent and coherent shared memory over mobile phones. 371-378
Processor Architecture 5
- Amer Qouneh, Zhongqi Li, Madhura Joshi, Wangyuan Zhang, Xin Fu, Tao Li:
Aurora: A thermally resilient photonic network-on-chip architecture. 379-386 - Lingda Li, Dong Tong, Zichao Xie, Junlin Lu, Xu Cheng:
Improving inclusive cache performance with two-level eviction priority. 387-392
Electronic Design Automation 5
- Mohamed Ismail, G. Edward Suh:
Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis. 393-400 - Taraneh Taghavi, Shyam Ramji, Frank Musante, Suhasini Rege:
Parameterized free space redistribution for engineering change in placement of integrated circuits. 401-406
Computer Systems 6
- Hanjoon Kim, John Kim
Providing cost-effective on-chip network bandwidth in GPGPUs. 407-412 - Randy Morris, Avinash Karanth Kodi, Ahmed Louri:
3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores. 413-418 - Daniel U. Becker, Nan Jiang, George Michelogiannakis
Adaptive Backpressure: Efficient buffer management for on-chip networks. 419-426 - Guang Sun, Chia-Wei Chang, Bill Lin, Lieguang Zeng:
Oblivious routing design for mesh networks to achieve a new worst-case throughput bound. 427-432
Test, Verification and Security 2
- Mostafa M. I. Taha, Patrick Schaumont
A novel profiled side-channel attack in presence of high Algorithmic Noise. 433-438 - Arnaldo Azevedo, Bart Vermeulen, Kees Goossens:
Architecture and design flow for a debug event distribution interconnect. 439-444 - Atena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic:
MSE minimization and fault-tolerant data fusion for multi-sensor systems. 445-452 - T. Nandha Kumar
Locating faults in application-dependent interconnects of SRAM based FPGAs. 453-459
Circuit Design 3
- Mineo Kaneko:
Timing-test scheduling for constraint-graph based post-silicon skew tuning. 460-465 - Andy Motten, Luc Claesen, Yun Pan:
Adaptive memory architecture for real-time image warping. 466-471 - Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González
A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance. 472-477
Posters
Logic and Circuit Design
- Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri
Engineering crossbar based emerging memory technologies. 478-479 - Jakob Lechner, Martin Lampacher:
Protecting pipelined asynchronous communication channels against single event upsets. 480-481
Computer Systems and Applications
- Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design. 482-483 - Justin Meza, Jing Li
A case for small row buffers in non-volatile main memories. 484-485 - Mickael Lanoe, Eric Senn:
Energy modelling of embedded multimedia streaming applications with GStreamer on heterogeneous MPSoC. 486-487 - Moo-Kyoung Chung, Yeon-Gon Cho, Soojung Ryu:
Efficient code compression for coarse grained reconfigurable architectures. 488-489 - Alena Simalatsar
Integration of correct-by-construction BIP models into the MetroII design space exploration flow. 490-491 - M. Binesh Marvasti, Ted H. Szymanski
The performance of hypermesh NoCs in FPGAs. 492-493 - Yingnan Cui, Wei Zhang
Distributed thermal-aware task scheduling for 3D Network-on-Chip. 494-495 - Richard Lee, Samar Abdi, Doug Regehr, Frederic Risacher:
System level modeling of real-time embedded software. 496-497
Processor Architecture
- George Razvan Voicu, Marius Enachescu
A 3D stacked high performance scalable architecture for 3D Fourier Transform. 498-499 - Kiyeon Lee, Moo-Kyoung Chung, Soojung Ryu, Yeon-Gon Cho, Sangyeun Cho:
Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors. 500-501 - Ahmad Lashgar
Dynamic warp resizing: Analysis and benefits in high-performance SIMT. 502-503
Electronic Design Automation
- Jin-Tai Yan, Zhi-Wei Chen:
Post-layout OPE-predicted redundant wire insertion for clock skew minimization. 504-505 - Qiong Zhao, Jiang Hu:
Track assignment considering crosstalk-induced performance degradation. 506-507 - Yiding Han, Koushik Chakraborty, Sanghamitra Roy
DOC: Fast and accurate congestion analysis for global routing. 508-509
Test, Verification and Security
- Leandro S. Freitas, Gabriel A. G. Andrade, Luiz C. V. dos Santos
Efficient verification of out-of-order behaviors with relaxed scoreboards. 510-511 - Jeongkyu Hong
ECC string: Flexible ECC management for low-cost error protection of L2 caches. 512-513 - Ahish Mysore Somashekar, Spyros Tragoudas, Sreenivas Gangadhar, Rathish Jayabharathi:
Non-enumerative generation of statistical path delays for ATPG. 514-515 - Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue:
Modeling economics of LSI design and manufacturing for test design selection. 516-517 - Jerry Backer, Ramesh Karri
Balancing performance and fault detection for GPGPU workloads. 518-519 - Shohreh Sharif Mansouri, Elena Dubrova:
Ring oscillator physical unclonable function with multi level supply voltages. 520-521 - Shohei Ono, Takeshi Matsumoto, Masahiro Fujita:
Automatic assertion extraction in gate-level simulation using GPGPUs. 522-523
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