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Simon W. Moore
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- affiliation: University of Cambridge, UK
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2020 – today
- 2024
- [j19]Alexandre Joannou, Peter Rugg, Jonathan Woodruff
, Franz A. Fuchs
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection. IEEE Des. Test 41(1): 40-49 (2024) - [j18]Robert N. M. Watson
CHERI: Hardware-Enabled C/C++ Memory Protection at Scale. IEEE Secur. Priv. 22(4): 50-61 (2024) - [c71]Nathaniel Wesley Filardo
Cornucopia Reloaded: Load Barriers for CHERI Heap Temporal Safety. ASPLOS (2) 2024: 251-268 - [c70]Peter Rugg, Jonathan Woodruff, Alexandre Joannou, Simon W. Moore:
A Suite of Processors to Explore CHERI-RISC-V Micro Architecture. DSD 2024: 351-360 - 2023
- [j17]Samuel W. Stark, A. Theodore Markettos, Simon W. Moore:
How Flexible Is CXL's Memory Protection? Commun. ACM 66(12): 46-51 (2023) - [j16]Richard Grisenthwaite
The Arm Morello Evaluation Platform - Validating CHERI-Based Security in a High-Performance System. IEEE Micro 43(3): 50-57 (2023) - [j15]Samuel W. Stark
How Flexible is CXL's Memory Protection?: Replacing a sledgehammer with a scalpel. ACM Queue 21(3): 54-64 (2023) - [j14]Andrew D. Brown
POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. ACM Trans. Parallel Comput. 10(2): 7:1-7:32 (2023) - [c69]Franz A. Fuchs, Jonathan Woodruff, Peter Rugg, Marno van der Maas, Alexandre Joannou, Alexander Richardson, Jessica Clarke, Nathaniel Wesley Filardo, Brooks Davis, John Baldwin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson:
Architectural Contracts for Safe Speculation. ICCD 2023: 578-586 - [c68]Mert Side, Brody Williams, John D. Leidel, Jonathan Woodruff, Simon W. Moore, Yong Chen:
Towards xBGAS on CHERI: Supporting a Secure Global Memory. IPDPS Workshops 2023: 578-581 - [c67]Saar Amar
CHERIoT: Complete Memory Safety for Embedded Devices. MICRO 2023: 641-653 - 2022
- [j13]Ashur Rafiev
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture. IET Comput. Digit. Tech. 16(2-3): 71-88 (2022) - [j12]Ashur Rafiev
Practical Distributed Implementation of Very Large Scale Petri Net Simulations. Trans. Petri Nets Other Model. Concurr. 16: 112-139 (2022) - [c66]Andrew Brown, Tim Todman, Wayne Luk, David B. Thomas
Non-deterministic event brokered computing. HEART 2022: 84-86 - [i2]Hesham Almatary, Michael Dodson, Jessica Clarke, Peter Rugg, Ivan Gomes, Michal Podhradsky, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson:
CompartOS: CHERI Compartmentalization for Embedded Systems. CoRR abs/2206.02852 (2022) - 2021
- [c65]Matthew Naylor, Simon W. Moore, David B. Thomas
General hardware multicasting for fine-grained message-passing architectures. PDP 2021: 126-133 - 2020
- [c64]Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas
Termination detection for fine-grained message-passing architectures. ASAP 2020: 17-24 - [c63]Marno van der Maas
Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation. CYSARM@CCS 2020: 1-12 - [c62]A. Theodore Markettos, John Baldwin, Ruslan Bukin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson:
Position Paper: Defending Direct Memory Access with CHERI Capabilities. HASP@MICRO 2020: 7:1-7:9 - [c61]Nathaniel Wesley Filardo
Cornucopia: Temporal Safety for CHERI Heaps. SP 2020: 608-625 - [c60]Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony C. J. Fox, Michael Roe, Brian Campbell
Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process. SP 2020: 1003-1020
2010 – 2019
- 2019
- [j11]A. Theodore Markettos, Robert N. M. Watson, Simon W. Moore, Peter Sewell, Peter G. Neumann:
Through computer architecture, darkly. Commun. ACM 62(6): 25-27 (2019) - [j10]Jonathan Woodruff
CHERI Concentrate: Practical Compressed Capabilities. IEEE Trans. Computers 68(10): 1455-1469 (2019) - [c59]Brooks Davis, Robert N. M. Watson, Alexander Richardson
CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment. ASPLOS 2019: 379-393 - [c58]Matthew Naylor, Simon W. Moore, David B. Thomas:
Tinsel: A Manythread Overlay for FPGA Clusters. FPL 2019: 375-383 - [c57]Hongyan Xia, Jonathan Woodruff
CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. MICRO 2019: 545-557 - [c56]A. Theodore Markettos, Colin Rothwell, Brett F. Gutstein, Allison Pearce, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson:
Thunderclap: Exploring Vulnerabilities in Operating System IOMMU Protection via DMA from Untrustworthy Peripherals. NDSS 2019 - 2018
- [c55]Hongyan Xia
CheriRTOS: A Capability Model for Embedded Devices. ICCD 2018: 92-99 - 2017
- [c54]David Chisnall
CHERI JNI: Sinking the Java Security Model into the C. ASPLOS 2017: 569-583 - [c53]Alexandre Joannou, Jonathan Woodruff
Efficient Tagged Memory. ICCD 2017: 641-648 - [c52]Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas
Programming Model to Develop Supercomputer Combinatorial Solvers. ICPP Workshops 2017: 171-179 - 2016
- [j9]Robert N. M. Watson, Robert M. Norton
Fast Protection-Domain Crossing in the CHERI Capability-System Architecture. IEEE Micro 36(5): 38-49 (2016) - [c51]A. Theodore Markettos, Simon W. Moore, Brian D. Jones, Roy Spliet, Vlad A. Gavrila:
Conquering the complexity mountain: Full-stack computer architecture teaching with FPGAs. EWME 2016: 1-6 - [c50]Matthew Naylor, Simon W. Moore, Alan Mujumdar:
A consistency checker for memory subsystem traces. FMCAD 2016: 133-140 - [i1]Robert N. M. Watson, Simon W. Moore, Peter G. Neumann:
CHERI: A Hardware-Software System to Support the Principle of Least Privilege. ERCIM News 2016(106) (2016) - 2015
- [c49]David Chisnall
Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine. ASPLOS 2015: 117-130 - [c48]Matthew Naylor, Simon W. Moore:
A generic synthesisable test bench. MEMOCODE 2015: 128-137 - [c47]Robert N. M. Watson, Jonathan Woodruff
CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization. IEEE Symposium on Security and Privacy 2015: 20-37 - 2014
- [j8]Yury Audzevich, Philip M. Watts, Andrew West, Alan Mujumdar, Simon W. Moore
Power Optimized Transceivers for Future Switched Networks. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2081-2092 (2014) - [c46]A. Theodore Markettos, Paul James Fox, Simon W. Moore
Interconnect for commodity FPGA clusters: Standardized or customized? FPL 2014: 1-8 - [c45]Matthew Naylor, Simon W. Moore
Rapid codesign of a soft vector processor and its compiler. FPL 2014: 1-4 - [c44]Jonathan Woodruff
The CHERI capability model: Revisiting RISC in an age of risk. ISCA 2014: 457-468 - [c43]Paul James Fox, A. Theodore Markettos, Simon W. Moore
Reliably prototyping large SoCs using FPGA clusters. ReCoSoC 2014: 1-8 - 2013
- [j7]Christian Fensch, Nick Barrow-Williams, Robert D. Mullins, Simon W. Moore
Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors. IEEE Trans. Computers 62(5): 914-928 (2013) - [c42]Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore
A spiking neural network on a portable FPGA tablet. FPL 2013: 1 - [c41]Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore
Managing the FPGA memory wall: Custom computing or vector processing? FPL 2013: 1-6 - [c40]Jonathan Woodruff
A 64-bit MIPS processor running freebsd on a portable FPGA tablet. FPL 2013: 1 - 2012
- [j6]Philip M. Watts, Simon W. Moore
Energy Implications of Photonic Networks With Speculative Transmission. JOCN 4(6): 503-513 (2012) - [c39]Simon W. Moore
Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation. FCCM 2012: 133-140 - [c38]Gregory A. Chadwick, Simon W. Moore
Mamba: A scalable communication centric multi-threaded processor architecture. ICCD 2012: 277-283 - 2010
- [j5]Danielle S. Bassett, Daniel Greenfield, Andreas Meyer-Lindenberg
Efficient Physical Embedding of Topologically Complex Information Processing Networks in Brains and Computer Circuits. PLoS Comput. Biol. 6(4) (2010) - [c37]Nick Barrow-Williams, Christian Fensch, Simon W. Moore
Proximity coherence for chip multiprocessors. PACT 2010: 123-134
2000 – 2009
- 2009
- [j4]Daniel Greenfield, Simon W. Moore
Implications of Electronics Technology Trends for Algorithm Design. Comput. J. 52(6): 690-698 (2009) - [j3]Arnab Banerjee, Pascal T. Wolkotte, Robert D. Mullins, Simon W. Moore
An Energy and Performance Exploration of Network-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 17(3): 319-329 (2009) - [c36]A. Theodore Markettos, Simon W. Moore
The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators. CHES 2009: 317-331 - [c35]Rosemary M. Francis, Simon W. Moore:
FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. FPGA 2009: 285 - [c34]Nick Barrow-Williams, Christian Fensch, Simon W. Moore
A communication characterisation of Splash-2 and Parsec. IISWC 2009: 86-97 - [c33]Arnab Banerjee, Simon W. Moore
Flow-aware allocation for on-chip networks. NOCS 2009: 183-192 - 2008
- [c32]Daniel Greenfield, Simon W. Moore:
Implications of Electronics Technology Trends to Algorithm Design. BCS Int. Acad. Conf. 2008: 331-342 - [c31]Philip Christopher Paul, Simon W. Moore
Tamper Protection for Security Devices. BLISS 2008: 92-96 - [c30]Rosemary M. Francis, Simon W. Moore
Exploring hard and soft networks-on-chip for FPGAs. FPT 2008: 261-264 - [c29]Rosemary M. Francis, Simon W. Moore, Robert D. Mullins:
A Network of Time-Division Multiplexed Wiring for FPGAs. NOCS 2008: 35-44 - [c28]Simon W. Moore
The next resource war: computation vs. communication. SLIP 2008: 81-86 - [c27]Daniel Greenfield, Simon W. Moore
Fractal communication in software data dependency graphs. SPAA 2008: 116-118 - 2007
- [c26]Robert D. Mullins, Simon W. Moore:
Demystifying Data-Driven and Pausible Clocking Schemes. ASYNC 2007: 175-185 - [c25]Arnab Banerjee, Robert D. Mullins, Simon W. Moore:
A Power and Energy Exploration of Network-on-Chip Architectures. NOCS 2007: 163-172 - [c24]Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance. NOCS 2007: 283-294 - 2006
- [c23]Kate Taylor, Simon W. Moore
My Compiler Really Understands Me: An Adaptive Programming Language Tutor. AH 2006: 389-392 - [c22]Robert D. Mullins, Andrew West, Simon W. Moore:
The design and implementation of a low-latency on-chip network. ASP-DAC 2006: 164-169 - [c21]Petros Oikonomakos, Jacques J. A. Fournier, Simon W. Moore
Implementing Cryptography on TFT Technology for Secure Display Applications. CARDIS 2006: 32-47 - [c20]Petros Oikonomakos, Simon W. Moore
An Asynchronous PLA with Improved Security Characteristics. DSD 2006: 257-264 - [c19]Jacques J. A. Fournier, Simon W. Moore
Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography. DSD 2006: 439-446 - [c18]Simon Hollis, Simon W. Moore
RasP: An Area-efficient, On-chip Network. ICCD 2006: 63-69 - [c17]Simon Hollis, Simon W. Moore:
An area-efficient, pulse-based interconnect. ISCAS 2006 - [c16]Kate Taylor, Simon W. Moore:
Adding question answering to an e-tutor for programming languages. SGAI Conf. (Applications) 2006: 193-206 - [c15]Simon Hollis, Simon W. Moore
An Asynchronous Interconnect Architecture for Device Security Enhancement. VLSI Design 2006: 209-215 - 2005
- [c14]Scott Fairbanks, Simon W. Moore:
Self-Timed Circuitry for Global Clocking. ASYNC 2005: 86-96 - [c13]Huiyun Li, A. Theodore Markettos, Simon W. Moore:
Security Evaluation Against Electromagnetic Analysis at Design Time. CHES 2005: 280-292 - [c12]Jacques J. A. Fournier, Simon W. Moore:
A Vector Approach to Cryptography Implementation. DRMTICS 2005: 277-297 - [c11]Huiyun Li, A. Theodore Markettos, Simon W. Moore
Security evaluation against electromagnetic analysis at design time. HLDVT 2005: 211-218 - 2004
- [c10]Scott Fairbanks, Simon W. Moore:
Analog Micropipeline Rings for High Precision Timing. ASYNC 2004: 41-50 - [c9]Robert D. Mullins, Andrew West, Simon W. Moore:
Low-Latency Virtual-Channel Routers for On-Chip Networks. ISCA 2004: 188-197 - 2003
- [j2]Simon W. Moore
Balanced self-checking asynchronous logic for smart card applications. Microprocess. Microsystems 27(9): 421-430 (2003) - [c8]Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor:
Security Evaluation of Asynchronous Circuits. CHES 2003: 137-151 - 2002
- [c7]George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson:
Point to Point GALS Interconnect. ASYNC 2002: 69-75 - [c6]Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor:
Improving Smart Card Security Using Self-Timed Circuits. ASYNC 2002: 211-218 - [c5]Panit Watcharawitch, Simon W. Moore:
JMA: The Java-Multithreading Architecture for Embedded Processors. ICCD 2002: 527- - 2001
- [c4]Simon W. Moore:
Protecting Consumer Security Devices. E-smart 2001: 1 - 2000
- [c3]George S. Taylor, Simon W. Moore
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. ASYNC 2000: 45-51 - [c2]Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson:
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. ICCD 2000: 73-78
1990 – 1999
- 1998
- [c1]Simon W. Moore, Peter Robinson:
Rapid prototyping of self-timed circuits. ICCD 1998: 360-365 - 1995
- [j1]Simon W. Moore, Brian T. Graham:
Tagged Up/Down Sorter - A Hardware Priority Queue. Comput. J. 38(9): 695-703 (1995)
Coauthor Index
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last updated on 2024-11-20 21:55 CET by the dblp team
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