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Phillip H. Jones
Phillip H. Jones III
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- affiliation: Iowa State University, Department of Electrical and Computer Engineering, Ames, IA, USA
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2020 – today
- 2024
- [c54]Alexis A. Aurandt
, Phillip H. Jones
Multimodal Model Predictive Runtime Verification for Safety of Autonomous Cyber-Physical Systems. FMICS 2024: 220-244 - 2023
- [c53]Chris Johannsen, Phillip H. Jones, Brian Kempa, Kristin Yvonne Rozier, Pei Zhang:
R2U2 Version 3.0: Re-Imagining a Toolchain for Specification, Resource Estimation, and Optimized Observer Generation for Runtime Verification in Hardware and Software. CAV (3) 2023: 483-497 - [c52]Diane T. Rover, Henry Duwe, Phillip H. Jones, Nicholas D. Fila, Mani Mina:
Case Studies in Applying Design Thinking to Course Design in Computer Engineering. FIE 2023: 1-9 - [c51]Chris Johannsen, Brian Kempa, Phillip H. Jones, Kristin Y. Rozier, Tichakorn Wongpiromsarn:
Impossible Made Possible: Encoding Intractable Specifications via Implied Domain Constraints. FMICS 2023: 151-169 - [c50]Gokul Hariharan
Maximum Satisfiability of Mission-Time Linear Temporal Logic. FORMATS 2023: 86-104 - [c49]Pei Zhang
Model Predictive Runtime Verification for Cyber-Physical Systems with Real-Time Deadlines. FORMATS 2023: 158-180 - 2022
- [j16]Abigail Hammer
Integrating runtime verification into an automated UAS traffic management system. Innov. Syst. Softw. Eng. 18(4): 567-580 (2022) - [c48]Gokul Hariharan
MLTL Multi-type (MLTLM): A Logic for Reasoning About Signals of Different Types. NSV/FoMLAS@CAV 2022: 187-204 - [c47]Henry Duwe, Diane T. Rover, Phillip H. Jones, Nicholas D. Fila, Mani Mina:
Defining and Supporting a Debugging Mindset in Computer Engineering Courses. FIE 2022: 1-9 - [c46]Alexis A. Aurandt
Runtime Verification Triggers Real-Time, Autonomous Fault Recovery on the CySat-I. NFM 2022: 816-825 - 2021
- [j15]Murad Qasaimeh
Benchmarking vision kernels and neural network inference accelerators on embedded platforms. J. Syst. Archit. 113: 101896 (2021) - [c45]Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones:
An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers. ASAP 2021: 250-257 - [c44]Diane T. Rover, Henry J. Duwe III, Mani Mina, Nicholas D. Fila, Phillip H. Jones, Lindsey S. Sleeth:
Learning and Professional Development Through Integrated Reflective Activities in Electrical and Computer Engineering Courses. FIE 2021: 1-9 - 2020
- [c43]Mohammad Pivezhandi, Phillip H. Jones, Joseph Zambreno:
ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation. ASAP 2020: 185-188 - [c42]Matthew Cauwels
Integrating Runtime Verification into an Automated UAS Traffic Management System. ECSA Companion 2020: 340-357 - [c41]Diane T. Rover, Nicholas D. Fila, Phillip H. Jones, Mani Mina:
Introducing Autonomy in an Embedded Systems Course Project. FIE 2020: 1-9 - [c40]Brian Kempa
Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2. FORMATS 2020: 196-214
2010 – 2019
- 2019
- [c39]Murad Qasaimeh
Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. FCCM 2019: 336 - [c38]Murad Qasaimeh
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. ICESS 2019: 1-8 - [i1]Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones:
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. CoRR abs/1906.11879 (2019) - 2018
- [j14]Alex Grieve
ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits. IEEE Trans. Computers 67(8): 1092-1104 (2018) - [c37]Murad Qasaimeh
A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors. FPL 2018: 351-354 - [c36]Joe Avey, Phillip H. Jones, Joseph Zambreno:
An FPGA-based Hardware Accelerator for Iris Segmentation. ReConFig 2018: 1-8 - [c35]Matthew Cauwels, Joseph Zambreno, Phillip H. Jones:
HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter. ReConFig 2018: 1-8 - 2017
- [j13]Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones:
The design and integration of a software configurable and parallelized coprocessor architecture for LQR control. J. Parallel Distributed Comput. 106: 121-131 (2017) - [c34]Pei Zhang, Joseph Zambreno, Phillip H. Jones:
An embedded scalable linear model predictive hardware-based controller using ADMM. ASAP 2017: 176-183 - [c33]Murad Qasaimeh
A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization. IPDPS Workshops 2017: 106-114 - 2016
- [j12]Chad Nelson, Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing. IEEE Trans. Parallel Distributed Syst. 27(10): 3029-3043 (2016) - [j11]Osama G. Attia
A Reconfigurable Architecture for the Detection of Strongly Connected Components. ACM Trans. Reconfigurable Technol. Syst. 9(2): 16:1-16:19 (2016) - [c32]Diane T. Rover, Joseph Zambreno, Mani Mina, Phillip H. Jones, Lora Leigh Chrystal:
Evidence-based planning to broaden the participation of women in electrical and computer engineering. FIE 2016: 1-7 - [c31]Aaron Mills, Phillip H. Jones, Joseph Zambreno:
Parameterizable FPGA-Based Kalman Filter Coprocessor Using Piecewise Affine Modeling. IPDPS Workshops 2016: 139-147 - 2015
- [j10]Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno
A Scalable Unsegmented Multiport Memory for FPGA-Based Systems. Int. J. Reconfigurable Comput. 2015: 826283:1-826283:12 (2015) - [j9]Tyler Johnson, Daniel Roggow, Phillip H. Jones, Joseph Zambreno:
An FPGA Architecture for the Recovery of WPA/WPA2 Keys. J. Circuits Syst. Comput. 24(7): 1550105:1-1550105:26 (2015) - [j8]Xinying Wang, Phillip H. Jones, Joseph Zambreno:
A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns. SIGARCH Comput. Archit. News 43(4): 76-81 (2015) - [j7]Adwait Gupte, Sudhanshu Vyas, Phillip H. Jones:
A Fault-Aware Toolchain Approach for FPGA Fault Tolerance. ACM Trans. Design Autom. Electr. Syst. 20(2): 32:1-32:22 (2015) - [c30]Kevin R. Townsend, Song Sun, Tyler Johnson, Osama G. Attia, Phillip H. Jones, Joseph Zambreno:
k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator. EIT 2015: 257-263 - [c29]Aaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones:
A software configurable coprocessor-based state-space controller. FPL 2015: 1-6 - [c28]Daniel Roggow, Paul Uhing, Phillip H. Jones, Joseph Zambreno:
A project-based embedded systems design course using a reconfigurable SoC platform. MSE 2015: 9-12 - [c27]Osama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno:
Accelerating all-pairs shortest path using a message-passing reconfigurable architecture. ReConFig 2015: 1-6 - [c26]Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones:
A software configurable and parallelized coprocessor architecture for LQR control. ReConFig 2015: 1-8 - 2014
- [j6]Sudhanshu Vyas, Chetan Kumar Ng, Joseph Zambreno, Christopher D. Gill, Ron Cytron, Phillip H. Jones:
An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis. IEEE Embed. Syst. Lett. 6(1): 4-7 (2014) - [j5]N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones:
Hardware-software architecture for priority queue management in real-time and embedded systems. Int. J. Embed. Syst. 6(4): 319-334 (2014) - [c25]N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones:
Cache design for mixed criticality real-time systems. ICCD 2014: 513-516 - [c24]Osama G. Attia, Tyler Johnson, Kevin Townsend, Phillip H. Jones, Joseph Zambreno:
CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search. IPDPS Workshops 2014: 228-235 - [c23]Xinying Wang, Phillip H. Jones, Joseph Zambreno:
A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach. ISVLSI 2014: 541-546 - [c22]Kevin Townsend, Phillip H. Jones, Joseph Zambreno:
A high performance systolic architecture for k-NN classification. MEMOCODE 2014: 201-204 - 2013
- [j4]Sudhanshu Vyas, Adwait Gupte, Christopher D. Gill, Ron K. Cytron
Hardware architectural support for control systems and sensor processing. ACM Trans. Embed. Comput. Syst. 13(2): 16:1-16:25 (2013) - [c21]Chetan Kumar Ng, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones:
Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms. ICCS 2013: 1891-1898 - [c20]Matt Rich, Nicola Elia, Phillip H. Jones:
Design and implementation of an H∞ controller for a quadrotor helicopter. MED 2013: 1189-1198 - 2012
- [j3]Song Sun, Madhu Monga, Phillip H. Jones, Joseph Zambreno:
An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 113-123 (2012) - [c19]Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno:
Design and evaluation of a delay-based FPGA Physically Unclonable Function. ICCD 2012: 143-146 - [c18]Chad Nelson, Kevin Townsend, Bhavani Satyanarayana Rao, Phillip H. Jones, Joseph Zambreno:
Shepard: A fast exact match short read aligner. MEMOCODE 2012: 91-94 - [c17]Chetan Kumar Ng, Sudhanshu Vyas, Jonathan A. Shidal, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones:
Improving System Predictability and Performance via Hardware Accelerated Data Structures. ICCS 2012: 1197-1205 - 2011
- [c16]Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno:
Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection. ICCD 2011: 289-292 - [c15]Michael Steffen, Phillip H. Jones, Joseph Zambreno:
Teaching graphics processing and architecture using a hardware prototyping approach. MSE 2011: 13-16 - [c14]Moinuddin Sayed, Phillip H. Jones:
Characterizing Non-ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-Based Thermometers. ReConFig 2011: 92-98 - [e1]Srinivas Aluru, Sanghamitra Bandyopadhyay, Ümit V. Çatalyürek, Devdatt P. Dubhashi, Phillip H. Jones, Manish Parashar, Bertil Schmidt:
Contemporary Computing - 4th International Conference, IC3 2011, Noida, India, August 8-10, 2011. Proceedings. Communications in Computer and Information Science 168, Springer 2011, ISBN 978-3-642-22605-2 [contents] - 2010
- [c13]Adwait Gupte, Phillip H. Jones:
An evaluation of a slice fault aware tool chain. DATE 2010: 1803-1808 - [c12]Michael Steffen, Veerendra Allada, Phillip H. Jones, Joseph Zambreno:
CANSCID-CUDA. MEMOCODE 2010: 95-98 - [c11]Sudhanshu Vyas, Pooja Mhapsekar, Aditya Ashok, Moinuddin Sayed, Avinash Srinivasa, Gunjan Pandey, Adam Jackson, Matthew Nelson, Anand Saggi, Harini Sundararaman, Phillip H. Jones:
Team [Ii][Ss][Uu][0-2]{4} design overview: MEMOCODE 2010 design contest. MEMOCODE 2010: 99-102
2000 – 2009
- 2009
- [c10]Adwait Gupte, Phillip H. Jones:
Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance. ReConFig 2009: 89-94 - [c9]Adwait Gupte, Phillip H. Jones:
Towards Hardware Support for Common Sensor Processing Tasks. RTCSA 2009: 85-90 - 2007
- [c8]Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood:
Changing Output Quality for Thermal Management. FCCM 2007: 353-354 - [c7]Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood:
Adaptive Thermoregulation for Applications on Reconfigurable Devices. FPL 2007: 246-253 - [c6]Phillip H. Jones, Young H. Cho, John W. Lockwood:
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads. VLSI Design 2007: 391-400 - 2006
- [c5]Phillip H. Jones, John W. Lockwood, Young H. Cho:
A Thermal Management and Profiling Method for Reconfigurable Hardware Applications. FPL 2006: 1-7 - [c4]Phillip H. Jones, Young H. Cho, John W. Lockwood:
An adaptive frequency control method using thermal feedback for reconfigurable hardware applications. FPT 2006: 229-236 - 2005
- [j2]Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood:
Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures. Int. J. Parallel Program. 33(2-3): 115-136 (2005) - [c3]Roger D. Chamberlain, John W. Lockwood, Saurabh Gayen, Richard Hough, Phillip H. Jones:
Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory. MSE 2005: 97-98 - 2004
- [j1]Keith Whisnant, Ravishankar K. Iyer, Zbigniew Kalbarczyk, Phillip H. Jones III, David A. Rennels, Raphael R. Some:
The Effects of an ARMOR-Based SIFT Environment on the Performance and Dependability of User Applications. IEEE Trans. Software Eng. 30(4): 257-277 (2004) - [c2]Phillip H. Jones, Shobana Padmanabhan, Daniel Rymarz, John Maschmeyer, David V. Schuehler, John W. Lockwood, Ron Cytron:
Liquid Architecture. IPDPS Next Generation Software Program - NSFNGS - PI Workshop 2004 - 2002
- [c1]David T. Stott, Phillip H. Jones III, M. Hamman, Zbigniew Kalbarczyk, Ravishankar K. Iyer:
NFTAPE: Networked Fault Tolerance and Performance Evaluator. DSN 2002: 542
Coauthor Index
Kristin Y. Rozier
aka: Kristin Yvonne Rozier
aka: Kristin Yvonne Rozier
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last updated on 2024-09-10 02:13 CEST by the dblp team
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