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Pedro López 0001
Pedro Juan López Rodríguez
Person information
- affiliation: Universitat Politècnica de València, Spain
- not to be confused with: Pedro López 0003
Other persons with the same name
- Pedro López 0002 — Technical University of Catalonia, Barcelona, Spain
- Pedro López 0003 — Departamento de Informática, Universidad de Valencia, Spain
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2020 – today
- 2025
- [j43]Pablo Andreu
, Sergi Alcaide
Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs. Future Gener. Comput. Syst. 163: 107518 (2025) - 2023
- [j42]Francisco J. Andújar
Energy efficient HPC network topologies with on/off links. Future Gener. Comput. Syst. 139: 126-138 (2023) - 2022
- [p1]Marco Aldinucci, David Atienza, Federico Bolelli
The DeepHealth Toolkit: A Key European Free and Open-Source Software for Deep Learning and Computer Vision Ready to Exploit Heterogeneous HPC and Cloud Architectures. Technologies and Applications for Big Data Value 2022: 183-202 - [i1]Pablo Andreu, Carles Hernández, Tomás Picornell, Pedro López, Sergi Alcaide
End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform. CoRR abs/2210.04683 (2022) - 2021
- [c100]Ilya Tuzov
Improving the Robustness of Redundant Execution with Register File Randomization. ICCAD 2021: 1-9
2010 – 2019
- 2019
- [j41]Francisco J. Andújar
Energy efficient torus networks with on/off links. J. Parallel Distributed Comput. 130: 37-49 (2019) - [j40]Francisco J. Andújar
POWAR: Power-Aware Routing in HPC Networks with On/Off Links. ACM Trans. Archit. Code Optim. 15(4): 61:1-61:22 (2019) - 2018
- [j39]Pedro López
Teaching high-performance service in a cluster computing course. J. Parallel Distributed Comput. 117: 138-147 (2018) - [c99]Francisco J. Andujar, Salvador Coll, Marina Alonso, Juan-Miguel Martínez, Pedro López, Francisco J. Alfaro, José L. Sánchez, Raúl Martínez:
Analyzing Topology Parameters for Achieving Energy-Efficient k-ary n-cubes. HiPINEB@HPCA 2018: 24-31 - 2017
- [j38]Roberto Peñaranda, María Engracia Gómez
A fault-tolerant routing strategy for k-ary n-direct s-indirect topologies based on intermediate nodes. Concurr. Comput. Pract. Exp. 29(13) (2017) - [j37]Pedro López
On a course on computer cluster configuration and administration. J. Parallel Distributed Comput. 105: 127-137 (2017) - [j36]Roberto Peñaranda, Crispín Gómez Requena, María Engracia Gómez
XOR-based HoL-blocking reduction routing mechanisms for direct networks. Parallel Comput. 67: 57-74 (2017) - 2016
- [j35]Francisco Almenar, Carlos Domínguez, Houcine Hassan, Juan-Miguel Martinez-Rubio, Pedro López:
Embedded GPU and multicore processors for emotional-based mobile robotic agents. Future Gener. Comput. Syst. 56: 192-201 (2016) - [j34]Roberto Peñaranda, Crispín Gómez Requena, María Engracia Gómez
The k-ary n-direct s-indirect family of topologies for large-scale interconnection networks. J. Supercomput. 72(3): 1035-1062 (2016) - [j33]Diego F. Bermúdez Garzón, Crispín Gómez Requena, María Engracia Gómez
A Family of Fault-Tolerant Efficient Indirect Topologies. IEEE Trans. Parallel Distributed Syst. 27(4): 927-940 (2016) - [c98]Roberto Peñaranda, Ernst Gunnar Gran
A New Fault-Tolerant Routing Methodology for KNS Topologies. HiPINEB@HPCA 2016: 1-8 - 2015
- [j32]Marina Alonso
Power consumption management in fat-tree interconnection networks. Parallel Comput. 48: 59-80 (2015) - [j31]Alejandro Valero
Design of Hybrid Second-Level Caches. IEEE Trans. Computers 64(7): 1884-1897 (2015) - [j30]Crispín Gómez Requena, Francisco Gilabert Villamón, María Engracia Gómez
A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies. J. Supercomput. 71(7): 2339-2364 (2015) - [c97]Abel Martinez, Carlos Domínguez, Houcine Hassan, Juan-Miguel Martinez-Rubio, Pedro López:
Using GPU and SIMD Implementations to Improve Performance of Robotic Emotional Processes. HPCC/CSS/ICESS 2015: 1876-1881 - [c96]Diego F. Bermúdez Garzón, Crispín Gómez Requena, Pedro López, María Engracia Gómez
Speeding-up the fault-tolerance analysis of interconnection networks. HPCS 2015: 160-167 - [c95]Roberto Peñaranda, Crispín Gómez Requena, María Engracia Gómez
XORAdap: A HoL-Blocking Aware Adaptive Routing Algorithm. PDP 2015: 48-52 - 2014
- [j29]Salvador Petit
Efficient Register Renaming and Recovery for High-Performance Processors. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1506-1514 (2014) - [c94]Roberto Peñaranda Cebrian, Crispín Gómez Requena, María Engracia Gómez Requena
HoL-Blocking Avoidance Routing Algorithms in Direct Topologies. HPCC/CSS/ICESS 2014: 11-18 - [c93]Diego F. Bermúdez Garzón, Crispín Gómez Requena, María Engracia Gómez
FT-RUFT: A Performance and Fault-Tolerant Efficient Indirect Topology. PDP 2014: 405-409 - 2013
- [j28]Rafael Ubal, Julio Sahuquillo
Hardware-Based Generation of Independent Subtraces of Instructions in Clustered Processors. IEEE Trans. Computers 62(5): 944-955 (2013) - [c92]Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. DATE 2013: 83-88 - [c91]Olav Lysne, Torsten Hoefler, Pedro López, Davide Bertozzi:
Topic 13: High-Performance Networks and Communication - (Introduction). Euro-Par 2013: 684 - [c90]Roberto Peñaranda, Crispín Gómez Requena, María Engracia Gómez, Pedro López, José Duato
Deterministic Routing with HoL-Blocking-Awareness for Direct Topologies. ICCS 2013: 2521-2524 - 2012
- [j27]Alejandro Valero
Combining recency of information with selective random and a victim cache in last-level caches. ACM Trans. Archit. Code Optim. 9(3): 16:1-16:20 (2012) - [j26]Alejandro Valero
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches. IEEE Trans. Computers 61(9): 1231-1242 (2012) - [j25]Joan-Lluís Ferrer, Elvira Baydal
Progressive Congestion Management Based on Packet Marking and Validation Techniques. IEEE Trans. Computers 61(9): 1296-1310 (2012) - [j24]José Flich
A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms. IEEE Trans. Parallel Distributed Syst. 23(3): 405-425 (2012) - [j23]Rafael Ubal, Julio Sahuquillo
A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions. IEEE Trans. Parallel Distributed Syst. 23(8): 1361-1368 (2012) - [j22]Alejandro Valero
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1108-1117 (2012) - [c89]Diego F. Bermúdez Garzón, Crispín Gómez Requena, María Engracia Gómez
Towards an Efficient Fat-Tree like Topology. Euro-Par 2012: 716-728 - [c88]Alejandro Valero
Analyzing the optimal ratio of SRAM banks in hybrid caches. ICCD 2012: 297-302 - [c87]Roberto Peñaranda, Crispín Gómez Requena, María Engracia Gómez
IODET: A HoL-blocking-aware Deterministic Routing Algorithm for Direct Topologies. ICPADS 2012: 702-703 - [c86]Roberto Peñaranda, Crispín Gómez Requena, María Engracia Gómez
A New Family of Hybrid Topologies for Large-Scale Interconnection Networks. NCA 2012: 220-227 - 2011
- [j21]Crispín Gómez Requena, María Engracia Gómez
How to reduce packet dropping in a bufferless NoC. Concurr. Comput. Pract. Exp. 23(1): 86-99 (2011) - [c85]Alejandro Valero
Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour. PACT 2011: 214 - [c84]Alejandro Valero
MRU-Tour-based Replacement Algorithms for Last-Level Caches. SBAC-PAD 2011: 112-119 - [r1]Pedro López:
Routing (Including Deadlock Avoidance). Encyclopedia of Parallel Computing 2011: 1749-1756 - 2010
- [j20]Marina Alonso, Salvador Coll, Juan-Miguel Martínez, Vicente Santonja, Pedro López, José Duato
Power saving in regular interconnection networks. Parallel Comput. 36(12): 696-712 (2010) - [c83]Rafael Ubal, Julio Sahuquillo
Exploiting subtrace-level parallelism in clustered processors. PACT 2010: 555-556 - [c82]Rafael Ubal, Julio Sahuquillo
Out-of-order retirement of instructions in sequentially consistent multiprocessors. ICCD 2010: 1-8 - [c81]Joan-Lluís Ferrer, Elvira Baydal
A Scalable and Early Congestion Management Mechanism for MINs. PDP 2010: 43-50
2000 – 2009
- 2009
- [j19]Rafael Ubal, Julio Sahuquillo, Salvador Petit
Power Reduction In Advanced Embedded IPC Processors. Intell. Autom. Soft Comput. 15(3): 495-507 (2009) - [j18]Salvador Petit Marti
A Complexity-Effective Out-of-Order Retirement Microarchitecture. IEEE Trans. Computers 58(12): 1626-1639 (2009) - [j17]Crispín Gómez Requena, María Engracia Gómez Requena
FT2EI: A Dynamic Fault-Tolerant Routing Methodology for Fat Trees with Exclusion Intervals. IEEE Trans. Parallel Distributed Syst. 20(6): 802-817 (2009) - [j16]Andres Mejia, Maurizio Palesi, José Flich
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Trans. Very Large Scale Integr. Syst. 17(3): 356-369 (2009) - [c80]Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. PACT 2009: 15-25 - [c79]Daniele Ludovici, Francisco Gilabert Villamón, Simone Medardoni, Crispín Gómez Requena, María Engracia Gómez
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints. DATE 2009: 562-565 - [c78]Salvador Petit
An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. DSD 2009: 635-642 - [c77]Rafael Ubal, Julio Sahuquillo
Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors. Euro-Par 2009: 309-320 - [c76]Salvador Petit
A power-aware hybrid RAM-CAM renaming mechanism for fast recovery. ICCD 2009: 150-157 - [c75]Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González
Boosting single-thread performance in multi-core systems through fine-grain multi-threading. ISCA 2009: 474-483 - [c74]Alejandro Valero
An hybrid eDRAM/SRAM macrocell to implement first-level data caches. MICRO 2009: 213-221 - 2008
- [j15]Crispín Gómez Requena, Francisco Gilabert Villamón, María Engracia Gómez, Pedro López, José Duato
Beyond Fat-tree: Unidirectional Load--Balanced Multistage Interconnection Network. IEEE Comput. Archit. Lett. 7(2): 49-52 (2008) - [c73]Noel Tomás, Julio Sahuquillo
Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot. Euro-Par 2008: 317-326 - [c72]Crispín Gómez Requena, María Engracia Gómez
Reducing Packet Dropping in a Bufferless NoC. Euro-Par 2008: 899-909 - [c71]Joan-Lluís Ferrer, Elvira Baydal
On the Influence of the Packet Marking and Injection Control Schemes in Congestion Management for MINs. Euro-Par 2008: 930-939 - [c70]Crispín Gómez Requena, Francisco Gilabert Villamón, María Engracia Gómez
RUFT: Simplifying the Fat-Tree Topology. ICPADS 2008: 153-160 - [c69]Crispín Gómez Requena, María Engracia Gómez
An Efficient Switching Technique for NoCs with Reduced Buffer Requirements. ICPADS 2008: 713-720 - [c68]Rafael Ubal, Julio Sahuquillo
The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures. IPDPS 2008: 1-11 - [c67]Francisco Gilabert Villamón, Simone Medardoni, Davide Bertozzi, Luca Benini, María Engracia Gómez, Pedro López, José Duato:
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. NOCS 2008: 107-116 - [c66]Crispín Gómez Requena, María Engracia Gómez
Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity. PDP 2008: 20-29 - 2007
- [c65]Rafael Ubal, Julio Sahuquillo, Salvador Petit
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. PACT 2007: 429 - [c64]Marina Alonso, Salvador Coll, Vicente Santonja, Juan-Miguel Martínez, Pedro López, José Duato:
Power-Aware Fat-Tree Networks Using On/Off Links. HPCC 2007: 472-483 - [c63]Rafael Ubal, Julio Sahuquillo
Leakage Current Reduction in Data Caches on Embedded Systems. IPC 2007: 45-50 - [c62]Crispín Gómez Requena, Francisco Gilabert Villamón, María Engracia Gómez
Deterministic versus Adaptive Routing in Fat-Trees. IPDPS 2007: 1-8 - [c61]Crispín Gómez Requena, María Engracia Gómez
An Efficient Fault-Tolerant Routing Methodology for Fat-Tree Interconnection Networks. ISPA 2007: 509-522 - [c60]José Flich
Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips. NOCS 2007: 183-194 - [c59]Joan-Lluís Ferrer, Elvira Baydal
Congestion Management in MINs through Marked and Validated Packets. PDP 2007: 254-261 - [c58]Rafael Ubal, Julio Sahuquillo
Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. SBAC-PAD 2007: 62-68 - 2006
- [j14]María Engracia Gómez
FIR: An efficient routing strategy for tori and meshes. J. Parallel Distributed Comput. 66(7): 907-921 (2006) - [j13]María Engracia Gómez, Pedro López, José Duato:
An Efficient Fault-Tolerant Routing Strategy for Tori and Meshes. Scalable Comput. Pract. Exp. 7(3) (2006) - [j12]María Engracia Gómez
A Routing Methodology for Achieving Fault Tolerance in Direct Networks. IEEE Trans. Computers 55(4): 400-415 (2006) - [c57]Gaspar Mora, José Flich
Towards an efficient switch architecture for high-radix switches. ANCS 2006: 11-20 - [c56]Francisco Gilabert Villamón, María Engracia Gómez
On the Influence of the Selection Function on the Performance of Fat-Trees. Euro-Par 2006: 864-873 - [c55]Marina Alonso, Salvador Coll, Juan-Miguel Martínez, Vicente Santonja, Pedro López, José Duato
Dynamic power saving in fat-tree interconnection networks using on/off links. IPDPS 2006 - [c54]Rafael Ubal, Julio Sahuquillo
Applying the zeros switch-off technique to reduce static energy in data caches. SBAC-PAD 2006: 133-140 - 2005
- [j11]Michihiro Koibuchi, Juan Carlos Martínez, José Flich
Enforcing in-order packet delivery in system area networks with adaptive routing. J. Parallel Distributed Comput. 65(10): 1223-1236 (2005) - [j10]Elvira Baydal
A Family of Mechanisms for Congestion Control in Wormhole Networks. IEEE Trans. Parallel Distributed Syst. 16(9): 772-784 (2005) - [c53]Marina Alonso, Juan-Miguel Martínez, Vicente Santonja, Pedro López, José Duato
Power Saving in Regular Interconnection Networks Built with High-Degree Switches. IPDPS 2005 - [c52]María Engracia Gómez
A Memory-Effective Routing Strategy for Regular Interconnection Networks. IPDPS 2005 - [c51]Juan Carlos Martínez, José Flich
In-Order Packet Delivery in Interconnection Networks using Adaptive Routing. IPDPS 2005 - [c50]María Engracia Gómez
A Memory-Effective Fault-Tolerant Routing Strategy for Direct Interconnection Networks. ISPDC 2005: 341-348 - 2004
- [j9]María Engracia Gómez
An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori. IEEE Comput. Archit. Lett. 3 (2004) - [c49]Marina Alonso, Juan-Miguel Martínez, Vicente Santonja, Pedro López:
Reducing Power Consumption in Interconnection Networks by Dynamically Adjusting Link Width. Euro-Par 2004: 882-890 - [c48]María Engracia Gómez
A New Adaptive Fault-Tolerant Routing Methodology for Direct Networks. HiPC 2004: 462-473 - [c47]Tor Skeie, Olav Lysne, José Flich, Pedro López, Antonio Robles, José Duato:
LASH-TOR: A Generic Transition-Oriented Routing Algorithm. ICPADS 2004: 595-604 - [c46]María Engracia Gómez
An Effective Fault-Tolerant Routing Methodology for Direct Networks. ICPP 2004: 222-231 - [c45]José Miguel Montañana
A Transition-Based Fault-Tolerant Routing Methodology for InfiniBand Networks. IPDPS 2004 - [c44]Nils Agne Nordbotten, María Engracia Gómez
A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes. NPC 2004: 341-356 - 2003
- [j8]Juan Carlos Martínez, José Flich
Supporting adaptive routing in IBA switches. J. Syst. Archit. 49(10-11): 441-456 (2003) - [j7]José Flich
Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing. IEEE Trans. Computers 52(9): 1134-1153 (2003) - [j6]Juan-Miguel Martinez-Rubio
FC3D: Flow Control-Based Distributed Deadlock Detection Mechanism for True Fully Adaptive Routing in Wormhole Networks. IEEE Trans. Parallel Distributed Syst. 14(8): 765-779 (2003) - [c43]Pedro López, José Flich, Antonio Robles:
Low-Fragmentation Mapping Strategies for Linear Forwarding Tables in InfiniBandTM. Euro-Par 2003: 947-957 - [c42]Elvira Baydal, Pedro López:
A Robust Mecahnism for Congestion Control: INC. Euro-Par 2003: 958-968 - [c41]José Carlos Sancho
Routing in InfiniBandTM Torus Network Topologie. ICPP 2003: 509-518 - [c40]Juan Carlos Martínez, José Flich
Supporting Fully Adaptive Routing in InfiniBand Networks. IPDPS 2003: 44 - [c39]María Engracia Gómez
VOQSW: A Methodology to Reduce HOL Blocking in InfiniBand Networks. IPDPS 2003: 46 - [c38]José Carlos Sancho
Performance Evaluation of COWs under Real Parallel Application. IPDPS 2003: 202 - [c37]Juan Carlos Martínez, José Flich
Supporting Adaptive Routing in InfiniBand Networks. PDP 2003: 165-172 - 2002
- [j5]José Flich
Boosting the Performance of Myrinet Networks. IEEE Trans. Parallel Distributed Syst. 13(7): 693-709 (2002) - [j4]José Flich
Boosting the Performance of Myrinet Networks. IEEE Trans. Parallel Distributed Syst. 13(11): 1166-1182 (2002) - [c36]María Engracia Gómez
Evaluation of Routing Algorithms for InfiniBand Networks (Research Note). Euro-Par 2002: 775-780 - [c35]Elvira Baydal, Pedro López, José Duato:
Congestion Control Based on Transmission Times. Euro-Par 2002: 781-790 - [c34]José Carlos Sancho
Effective Methodology for Deadlock-Free Minimal Routing in InfiniBand Networks. ICPP 2002: 409-418 - [c33]José Carlos Sancho, José Flich
Analyzing the Influence of Virtual Lanes on the Performance of InfiniBand Networks. IPDPS 2002 - [c32]Elvira Baydal
Avoiding Network Congestion with Local Information. ISHPC 2002: 35-48 - [c31]José Flich
Improving InfiniBand Routing through Multiple Virtual Networks. ISHPC 2002: 49-63 - [c30]Elvira Baydal
Increasing the Adaptivity of Routing Algorithms for k-ary n-cubes. PDP 2002: 455-462 - [c29]José Flich, Manuel P. Malumbres, Pedro López, José Duato
Removing the Latency Overhead of the ITB Mechanism in COWs with Source Routing. PDP 2002: 463-470 - 2001
- [j3]Juan-Miguel Martinez-Rubio
A Cost-Effective Approach to Deadlock Handling in Wormhole Networks. IEEE Trans. Parallel Distributed Syst. 12(7): 716-729 (2001) - [c28]Pedro López, José Flich
Deadlock-Free Routing in InfiniBand through Destination Renaming. ICPP 2001: 427-436 - [c27]José Flich
Improving Network Performance by Reducing Network Contention in Source-Based COWs with a Low Path-Computation Overhead. IPDPS 2001: 70 - [c26]Salvador Coll, José Flich
A First Implementation of In-Transit Buffers on Myrinet GM Software. IPDPS 2001: 162 - [c25]Elvira Baydal
A Congestion Control Mechanism for Wormhole Networks. PDP 2001: 19-26 - 2000
- [c24]José Flich
Improving the Performance of Regular Networks with Source Routing. ICPP 2000: 353-361 - [c23]José Flich
Performance evaluation of a new routing strategy for irregular networks with source routing. ICS 2000: 34-43 - [c22]José Flich, Manuel P. Malumbres
Improving Routing Performance in Myrinet Networks. IPDPS 2000: 27-32 - [c21]Elvira Baydal, Pedro López, José Duato
A Simple and Efficient Mechanism to Prevent Saturation in Wormhole Networks. IPDPS 2000: 617-622 - [c20]Juan Carlos Martínez, Federico Silla, Pedro López, José Duato:
On the Influence of the Selection Function on the Performance of Networks of Workstations. ISHPC 2000: 292-299 - [c19]José Flich
Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing. ISHPC 2000: 300-309
1990 – 1999
- 1999
- [c18]Juan-Miguel Martínez, Pedro López, José Duato:
Impact of Buffer Size on the Efficiency of Deadlock Detection. HPCA 1999: 315-318 - [c17]José Flich, Manuel P. Malumbres
Performance Evaluation of Networks of Workstations with Hardware Shared Memory Model Using Execution-Driven Simulation. ICPP 1999: 146-153 - [c16]Pedro López, Rosa Alcover, José Duato
Optimizing network throughput: optimal versus robust design. PDP 1999: 45-52 - 1998
- [j2]Pedro López, Rosa Alcover, José Duato
A cost-effective methodology for the evaluation of interconnection networks. J. Syst. Archit. 44(9-10): 815-830 (1998) - [c15]José Flich
Edinet: An Execution Driven Interconnection Network Simulator for DSM Systems. Computer Performance Evaluation (Tools) 1998: 336-339 - [c14]Pedro López, Juan-Miguel Martínez, José Duato:
A Very Efficient Distributed Deadlock Detection Mechanism for Wormhole Networks. HPCA 1998: 57-66 - [c13]Pedro López, Juan-Miguel Martínez, José Duato
DRIL: Dynamically Reduced Message Injection Limitation Mechanism for Wormhole Networks. ICPP 1998: 535-542 - [c12]Pedro López, José Duato
A lab course on computer architecture. WCAE@ISCA 1998: 11 - 1997
- [c11]Federico Silla, Manuel P. Malumbres
Efficient Adaptive Routing in Networks of Workstations with Irregular Topology. CANPC 1997: 46-60 - [c10]Fabrizio Petrini, José Duato, Pedro López, Juan-Miguel Martínez:
LIFE: a limited injection, fully adaptive, recovery-based routing algorithm. HiPC 1997: 316-321 - [c9]Juan-Miguel Martínez, Pedro López, José Duato, Timothy Mark Pinkston:
Software-Based Deadlock Recovery Technique for True Fully Adaptive Routing in Wormhole Networks. ICPP 1997: 182-189 - [c8]José Duato, Pedro López, Sudhakar Yalamanchili:
Deadlock- and Livelock-Free Routing Protocols for Wave Switching. IPPS 1997: 570-577 - [c7]Pedro López, Juan-Miguel Martínez, José Duato, Fabrizio Petrini:
On the Reduction of Deadlock Frequency by Limiting Message Injection in Wormhole Networks. PCRCW 1997: 295-307 - 1996
- [c6]José Duato
A High Performance Router Architecture for Interconnection Networks. ICPP, Vol. 1 1996: 61-68 - [c5]Rosa Alcover, Pedro López, José Duato
Interconnection Network Design: A Statistical Analysis of Interactions between Factors. PDP 1996: 211-218 - 1995
- [j1]Pedro López, José Duato:
Deadlock-Free Fully-Adaptive Minimal Routing Algorithms: Limitations and Solutions. Comput. Artif. Intell. 14(2): 105-125 (1995) - 1994
- [c4]José Duato
Highly adaptive wormhole routing algorithms for N-dimensional torus. Interconnection Networks and Mapping and Scheduling Parallel Computations 1994: 87-104 - [c3]José Duato, Pedro López:
Performance Evaluation of Adaptive Routing Algorithms for k-ary-n-cubes. PCRCW 1994: 45-59 - [c2]José Duato Marín
Bandwidth Requirements For Wormhole Switches: A Simple And Efficient Design. PDP 1994: 377-384 - 1993
- [c1]Pedro López, José Duato:
Deadlock-Free Adaptive Routing Algorithms for the 3D-Torus: Limitations and Solutions. PARLE 1993: 684-687
Coauthor Index
José Duato
aka: José Duato Marín
aka: José Duato Marín
[j34] [j33] [j31] [j30] [c94] [c93] [j28] [c92] [c90] [j27] [j26] [j25] [j24] [j22] [c89] [c88] [c87] [c86] [j21] [c85] [c84] [j20] [c83] [c81] [j18] [j16] [c78] [c74] [j15] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c62] [c61] [c60] [c59] [j14] [j13] [j12] [c57] [c56] [c55] [j11] [j10] [c53] [c52] [c51] [c50] [j9] [c48] [c47] [c46] [c45] [c44] [j8] [j7] [j6] [c41] [c40] [c39] [c38] [c37] [j5] [j4] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [j3] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [j2] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [j1] [c4] [c3] [c2] [c1]
María Engracia Gómez
aka: María Engracia Gómez Requena
aka: María Engracia Gómez Requena
Roberto Peñaranda
aka: Roberto Peñaranda Cebrian
aka: Roberto Peñaranda Cebrian
Salvador Petit
aka: Salvador Petit Marti
aka: Salvador Petit Marti
Julio Sahuquillo
aka: Julio Sahuquillo Borrás
aka: Julio Sahuquillo Borrás
Rafael Ubal
aka: Rafael Ubal Tena
aka: Rafael Ubal Tena
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last updated on 2024-10-23 21:27 CEST by the dblp team
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