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17th DDECS 2014: Warsaw, Poland
- 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-4560-3
- A. Mehdaoui, J. Pagazani, G. Schropfer, Gaëlle Lissorgues:
SiP design flow and 3D DRC for MEMS. 12-13 - Stefano Pettazzi, Andrew Plews, Anatoly Rudenko, Ahmed Nejim:
Development of 3D space partitioning and design rule check for smart system solutions. 14 - Muhammad Aamir Khan, Hans G. Kerkhoff:
Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs. 15-20 - Jan Malburg, Niklas Krafczyk, Görschwin Fey
:
Automatically connecting hardware blocks via light-weight matching techniques. 21-26 - Andrzej Abramowski
A double-path intra prediction architecture for the hardware H.265/HEVC encoder. 27-32 - Jürgen Maier
Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic. 33-38 - Albert Au, Artur Pogiel, Janusz Rajski, Piotr Sydow, Jerzy Tyszer, Justyna Zawada:
Quality assurance in memory built-in self-test tools. 39-44 - Marcel Baláz, Stefan Kristofík
Generic built-in self-repair architectures for SoC logic cores. 45-50 - Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng:
A 64-MHz∼640-MHz 64-phase clock generator. 51-54 - Woo-Rham Bae
A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology. 55-58 - Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada:
Burst-pulse Generator based on transmission line toward sub-MMW. 59-64 - Jing Ning, Klaus Hofmann:
A 120V high voltage DAC array for a tunable antenna in communication system. 65-70 - Tariq Bashir Ahmad, Maciej J. Ciesielski:
Fast time-parallel C-based event-driven RTL simulation. 71-76 - Raimund Ubar
Lower bounds of the size of Shared Structurally Synthesized BDDs. 77-82 - Roel Jordans, Erkan Diken, Lech Józwiak, Henk Corporaal:
BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching. 83-88 - Harish Balasubramaniam, Klaus Hofmann:
Analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators. 89-92 - Andrzej Grodzicki, Witold A. Pleskacz:
Multistage low ripple charge pump. 93-98 - Juraj Brenkus, Viera Stopjaková
A novel impedance calculation method and its time efficiency evaluation. 99-103 - Ondrej Novák, Jiri Jenícek, Martin Rozkovec
Test-data compression with low number of channels and short test time. 104-109 - Panagiotis Sismanoglou, Dimitris Nikolos:
Test data compression based on reuse and bit-flipping of parts of dictionary entries. 110-115 - Carolina Metzler, Aida Todri-Sanial
Timing-aware ATPG for critical paths with multiple TSVs. 116-121 - Pranab Roy, Hafizur Rahaman
A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips. 122-128 - Eleonora Schönborn, Kamalika Datta, Robert Wille
Optimizing DD-based synthesis of reversible circuits using negative control lines. 129-134 - Zdenek Vasícek, Lukás Sekanina:
Evolutionary design of approximate multipliers under different error metrics. 135-140 - Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila
Online testing of many-core systems in the Dark Silicon era. 141-146 - Ronaldo Rodrigues Ferreira, Thomas Klotz, Thilo Vörtler, Jean da Rolt, Gabriel L. Nazar, Álvaro Freitas Moreira, Luigi Carro, Karsten Einwich:
Reliable execution of statechart-generated correct embedded software under soft errors. 147-152 - Tobias Koal, Mario Schölzel, Heinrich Theodor Vierhaus:
Combining fault tolerance and self repair at minimum cost in power and hardware. 153-158 - Dominik Macko
Self-managing power management unit. 159-162 - Yo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang:
A low supply voltage synchronous mirror delay with quadrature phase output. 163-166 - Salma Hesham, Mohamed A. Abd El Ghany
High throughput architecture for the Advanced Encryption Standard Algorithm. 167-170 - Lukas Miculka, Zdenek Kotásek:
Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA. 171-174 - Milan Dvorak, Jan Korenek:
Low latency book handling in FPGA for high frequency trading. 175-178 - Tomás Závodník, Lukas Kekely
CRC based hashing in FPGA using DSP blocks. 179-182 - Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda:
The LSI implementation of a memory based field programmable device for MCU peripherals. 183-188 - Viktor Pus, Lukas Kekely
Design methodology of configurable high performance packet parser for FPGA. 189-194 - Pawel Dabal
A study on fast pipelined pseudo-random number generator based on chaotic logistic map. 195-200 - Steffen Ostendorff, Jorge H. Meza Escobar, Heinz-Dietrich Wuttke
Modeling timing constraints for automatic generation of embedded test instruments. 201-206 - Anu Asokan, Aida Todri-Sanial
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. 207-212 - Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri
Test and diagnosis of power switches. 213-218 - Lukas Kekely
Fast lookup for dynamic packet filtering in FPGA. 219-222 - Imran Wali, Arnaud Virazel
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. 223-225 - Lufei Shen, Ferdinand Keil, Klaus Hofmann:
Stabilization methods for integrated high voltage charge pumps. 226-229 - Mikolaj Roszkowski, Grzegorz Pastuszak
FPGA design of the computation unit for the semi-global stereo matching algorithm. 230-233 - Martin Krammer, Michael Karner, Anton Fuchs:
System design for enhanced forward-engineering possibilities of safety critical embedded systems. 234-237 - Piotr Maj
Mismatch effects and their correction in large area ASICs. 238-241 - Panagiotis Chaourani, Spyridon Nikolaidis
A unified CMOS inverter model for planar and FinFET nanoscale technologies. 242-245 - Victor Tomashevich, Christina Gimmler-Dumont, Christian Fesl, Norbert Wehn
A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. 246-249 - Peter Malík:
Dedicated hardware architecture for object tracking preprocessing implemented in FPGA. 250-253 - Omar Abdelmalek, David Hély
Emulation based fault injection on UHF RFID transponder. 254-257 - Petr Fiser, Jan Schmidt, Jiri Balcarek:
Sources of bias in EDA tools and its influence. 258-261 - Zoran Stamenkovic
Automatic and reliable electrical characterization of MOSFETs. 262-265 - Martin Kovác
An approach towards selection of the oscillation frequency for oscillation test of analog ICs. 266-267 - Domenico Bertoncelli, Pasquale Caianiello
Customer return detection with features selection. 268-269 - Tomasz Garbolino:
Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections. 270-273 - Vlastimil Kosar
On NFA-split architecture optimizations. 274-277 - Piotr Otfinowski
ADCs in deep submicron technologies for ASICs of pixel architecture. 278-281 - Kevin Ngari Muriithi, Toru Nakura, Kunihiro Asada:
Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. 282-285 - Marco Gaudesi, S. Saleem, Ernesto Sánchez, Matteo Sonza Reorda
On the in-field test of Branch Prediction Units using the correlated predictor mechanism. 286-289 - Grzegorz Pastuszak
FPGA architectures of the quantization and the dequantization for video encoders. 290-293 - Nam-Khanh Dang
An efficient hardware architecture for inter-prediction in H.264/AVC encoders. 294-297 - Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial
An intra-cell defect grading tool. 298-301 - Andrzej Wielgus
Heuristic algorithm of two-level minimization of fuzzy logic functions. 302-305 - Hafiz ul Asad
Verifying robust frequency domain properties of non linear oscillators using SMT. 306-309 - Vasileios Gerakis, Christina Avdikou, Alexandros Liolios, Alkis A. Hatzopoulos
Modeling and analysis of cracked through silicon via (TSV) interconnections. 310-313 - Andrej Kincel, Marcel Baláz:
Case study: BISR for a processor multiplier. 314-317 - Pavel Fiala
Efficient VHDL implementation of symbol synchronization for software radio based on FPGA. 318-321
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