default search action
Lech Józwiak
Person information
- affiliation: Eindhoven University of Technology, Netherlands
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
- [j45]Lech Józwiak, Francesco Leporati:
Editorial: Recent developments and the future of MICPRO. Microprocess. Microsystems 98: 104754 (2023) - 2021
- [c89]Yahya Jan, Lech Józwiak:
Quality-driven Design of Deep Neural Network Accelerators for CPS and IoT Applications. MECO 2021: 1-6
2010 – 2019
- 2018
- [c88]Tong Geng, Erkan Diken, Tianqi Wang, Lech Józwiak, Martin C. Herbordt:
An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures. HPEC 2018: 1-7 - 2017
- [j44]Lech Józwiak:
Advanced mobile and wearable systems. Microprocess. Microsystems 50: 202-221 (2017) - [j43]Roel Jordans, Lech Józwiak, Henk Corporaal, Rosilde Corvino:
Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. Microprocess. Microsystems 51: 114-133 (2017) - [j42]Radovan Stojanovic, Lech Józwiak:
Special issue on cyber-physical systems. Microprocess. Microsystems 52: 219-220 (2017) - 2016
- [j41]Francesco Leporati, Lech Józwiak:
Special Section on European Projects in Embedded System Design 2015. Microprocess. Microsystems 47: 251 (2016) - [c87]Lech Józwiak, Radovan Stojanovic, Budimir Lutovac
:
Message from the chairs. MECO 2016: 1-2 - [c86]Lech Józwiak:
Wearable and mobile systems. MECO 2016: 7-9 - 2015
- [j40]Francesco Leporati, Lech Józwiak:
MICPRO special issue on European projects in embedded system design 2014. Microprocess. Microsystems 39(8): 1157 (2015) - [c85]Erkan Diken, Martin J. O'Riordan, Roel Jordans, Lech Józwiak, Henk Corporaal, David Moloney:
Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths. ASAP 2015: 181-188 - [c84]David Perlaza, Adam Postula, Lech Józwiak, Tadeusz A. Wysocki:
FPGA-accelerated simulation engine for non-viral gene delivery. ICSPCS 2015: 1-5 - [c83]Erkan Diken, Lech Józwiak:
A compilation technique and performance profits for VLIW with heterogeneous vectors. MECO 2015: 9-12 - 2014
- [j39]Yahya Jan, Lech Józwiak:
Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding. Microprocess. Microsystems 38(2): 152-169 (2014) - [j38]Francesco Leporati, Lech Józwiak:
Preface. Microprocess. Microsystems 38(8): 920 (2014) - [j37]Erkan Diken, Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal, Felipe Augusto Chies:
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths. Microprocess. Microsystems 38(8): 947-959 (2014) - [c82]Roel Jordans, Erkan Diken, Lech Józwiak, Henk Corporaal:
BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching. DDECS 2014: 83-88 - [c81]Alexandre Solon Nery, Nadia Nedjah
A framework for automatic custom instruction identification on multi-issue ASIPs. INDIN 2014: 428-433 - [c80]Alexandre Solon Nery, Nadia Nedjah
Automatic complex instruction identification for efficient application mapping onto ASIPs. LASCAS 2014: 1-4 - [c79]Roel Jordans, Lech Józwiak, Henk Corporaal:
Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm. MECO 2014: 32-35 - [c78]Erkan Diken, Roel Jordans, Lech Józwiak, Henk Corporaal:
Construction and exploitation of VLIW asips with multiple vector-widths. MECO 2014: 244-247 - 2013
- [j36]Nadia Nedjah
Application-specific processors and system-on-chips for embedded and pervasive applications. Microprocess. Microsystems 37(6-7): 672-673 (2013) - [j35]Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah
Hardware reuse in modern application-specific processors and accelerators. Microprocess. Microsystems 37(6-7): 684-692 (2013) - [j34]Alexandre Solon Nery, Nadia Nedjah
Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs. Microprocess. Microsystems 37(6-7): 739-749 (2013) - [j33]Francesco Leporati, Lech Józwiak:
Preface. Microprocess. Microsystems 37(8-C): 965 (2013) - [j32]Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni
ASAM: Automatic architecture synthesis and application mapping. Microprocess. Microsystems 37(8-C): 1002-1019 (2013) - [j31]Lech Józwiak, Yahya Jan:
Design of massively parallel hardware multi-processors for highly-demanding embedded applications. Microprocess. Microsystems 37(8-D): 1155-1172 (2013) - [c77]Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal:
Exploring processor parallelism: Estimation methods and optimization strategies. DDECS 2013: 18-23 - [c76]Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal:
An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors. DSD 2013: 471-474 - [c75]Alexandre Solon Nery, Nadia Nedjah
A Reconfigurable Ray-Tracing Multi-Processor SoC with Hardware Replication-Aware Instruction Set Extension. ICA3PP (1) 2013: 346-356 - [c74]Lech Józwiak:
HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications. ISVLSI 2013: 145-146 - [c73]Lech Józwiak, Yahya Jan:
Hardware Multi-processor Design for Highly-Demanding Applications. ITNG 2013: 200-205 - [c72]Lech Józwiak, Jan Madsen
Quality-driven model-based design of multi-processor embedded systems for highlydemanding applications. MECO 2013: 1-3 - [c71]Lech Józwiak, Radovan Stojanovic, Budimir Lutovac
Message from the chairs. MECO 2013: 1-2 - [c70]Erkan Diken, Rosilde Corvino, Lech Józwiak:
Rapid and accurate energy estimation of vector processing in VLIW ASIPs. MECO 2013: 33-37 - [c69]Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal:
Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs. MECO 2013: 38-41 - [c68]Laura Micconi, Rosilde Corvino, Deepak Gangadharan
Hierarchical DSE for multi-ASIP platforms. MECO 2013: 50-53 - 2012
- [j30]Yahya Jan, Lech Józwiak:
Scalable communication architectures for massively parallel hardware multi-processors. J. Parallel Distributed Comput. 72(11): 1450-1463 (2012) - [j29]Yahya Jan, Lech Józwiak:
Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors. VLSI Design 2012: 794753:1-794753:20 (2012) - [c67]Roel Jordans, Rosilde Corvino, Lech Józwiak:
Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors. DSD 2012: 152-155 - [c66]Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni
ASAM: Automatic Architecture Synthesis and Application Mapping. DSD 2012: 216-225 - [c65]Rosilde Corvino, Erkan Diken, Abdoulaye Gamatié, Lech Józwiak:
Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study. DSD 2012: 774-781 - [c64]Rosilde Corvino, Abdoulaye Gamatié, Marc Geilen
Design space exploration in application-specific hardware synthesis for multiple communicating nested loops. ICSAMOS 2012: 128-135 - [c63]Alexandre Solon Nery, Nadia Nedjah
Interactive Volume Rendering Based on Ray-Casting for Multi-core Architectures. VECPAR 2012: 177-186 - 2011
- [c62]Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah
Hardware Reuse in Modern Application-Specific Processors and Accelerators. DSD 2011: 140-147 - [c61]Alexandre Solon Nery, Nadia Nedjah
A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations. DSD 2011: 511-518 - [c60]Michal Bryk, Lech Józwiak, Wieslaw Kuzmicz
Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits. DSD 2011: 685-692 - [c59]Alexandre Solon Nery, Nadia Nedjah
Massively Parallel Identification of Intersection Points for GPGPU Ray Tracing. ICA3PP (2) 2011: 14-23 - [c58]Alexandre Solon Nery, Nadia Nedjah
A parallel architecture for ray-tracing with an embedded intersection algorithm. ISCAS 2011: 1491-1494 - [c57]Lech Józwiak, Menno Lindwer:
Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs. PDP 2011: 483-487 - [c56]Lech Józwiak:
Advanced Architectures for Highly-demanding Embedded and Pervasive Applications. PECCS 2011: 09-014 - 2010
- [j28]Lech Józwiak, Nadia Nedjah
Modern development methods and tools for embedded reconfigurable systems: A survey. Integr. 43(1): 1-33 (2010) - [c55]Lech Józwiak, Yahya Jan:
Quality-driven methodology for demanding accelerator design. ISQED 2010: 380-389 - [c54]Lech Józwiak, Yahya Jan:
Architecture Design of Reconfigurable Accelerators for Demanding Applications. ITNG 2010: 1201-1206 - [c53]Lech Józwiak:
Quality-driven SoC architecture synthesis for embedded applications. SoCC 2010: 425-426
2000 – 2009
- 2009
- [j27]Lech Józwiak, Nadia Nedjah
Modern Architectures for Embedded Reconfigurable Systems - a Survey. J. Circuits Syst. Comput. 18(2): 209-254 (2009) - [c52]Yahya Jan, Lech Józwiak:
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia. ARC 2009: 342-348 - [c51]Yahya Jan, Lech Józwiak:
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. SAMOS 2009: 24-35 - 2008
- [j26]Venkatesan Muthukumar, Lech Józwiak:
Editorial. J. Syst. Archit. 54(3-4): 347-348 (2008) - [j25]Lech Józwiak, Sien-An Ong:
Quality-driven model-based architecture synthesis for real-time embedded SoCs. J. Syst. Archit. 54(3-4): 349-368 (2008) - [c50]Lech Józwiak, Szymon Bieganski:
Technology Library Modelling for Information-driven Circuit Synthesis. DSD 2008: 480-489 - [c49]Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk:
High-Quality Circuit Synthesis for Modern Technologies. ISQED 2008: 168-173 - [c48]Lech Józwiak, Alexander Douglas:
Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators. ITNG 2008: 1123-1130 - 2007
- [c47]Srikanth Venkataraman, Nagesh Nagapalli, Lech Józwiak:
Quality Driven Manufacturing and SOC Designs. ISQED 2007: 5 - [c46]Lech Józwiak:
Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCs. ISQED 2007: 6 - 2006
- [c45]Lech Józwiak:
Life-Inspired Systems and Their Quality-Driven Design. ARCS 2006: 1-16 - [c44]Lech Józwiak, Aleksander Slusarczyk, Dominik Gawlowski:
Multi-objective Optimal FSM State Assignment. DSD 2006: 385-396 - [c43]Lech Józwiak, Sien-An Ong:
Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs. DSD 2006: 397-406 - [c42]Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk:
Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems. ICSAMOS 2006: 177-184 - 2005
- [j24]Henry Selvaraj, Lech Józwiak:
Reconfigurable embedded systems: Synthesis, design and application. J. Syst. Archit. 51(6-7): 347-349 (2005) - [j23]Lech Józwiak, Szymon Bieganski, Artur Chojnacki:
Information-driven circuit synthesis with the pre-characterized gate libraries. J. Syst. Archit. 51(6-7): 405-423 (2005) - [c41]Lech Józwiak, Szymon Bieganski:
High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. DSD 2005: 450-459 - [c40]Lech Józwiak, Kaustav Banerjee:
Plenary Session 2P. ISQED 2005: 461 - [c39]Lech Józwiak:
Life-Inspired Systems: Assuring Quality in the Era of Complexity, invited. IWSOC 2005: 139-142 - 2004
- [j22]Lech Józwiak, Aleksander Slusarczyk:
General decomposition of incompletely specified sequential machines with multi-state behavior realization. J. Syst. Archit. 50(8): 445-492 (2004) - [c38]Lech Józwiak:
Life-Inspired Systems. DSD 2004: 36-43 - [c37]Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk:
An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods. DSD 2004: 160-167 - [c36]Lech Józwiak, Szymon Bieganski:
Information Trans-Coders in Information-Driven Circuit Synthesis. DSD 2004: 288-397 - 2003
- [j21]Lech Józwiak:
Advanced AI Search Techniques in Modern Digital Circuit Synthesis. Artif. Intell. Rev. 20(3-4): 269-318 (2003) - [j20]Martyn Edwards, Lech Józwiak:
Special-issue on reconfigurable systems. J. Syst. Archit. 49(4-6): 123-125 (2003) - [j19]Lech Józwiak, Aleksander Slusarczyk, Artur Chojnacki:
Fast and compact sequential circuits for the FPGA-based reconfigurable systems. J. Syst. Archit. 49(4-6): 227-246 (2003) - [j18]Lech Józwiak, Artur Chojnacki:
Effective and efficient FPGA synthesis through general functional decomposition. J. Syst. Archit. 49(4-6): 247-265 (2003) - [j17]Martyn Edwards, Lech Józwiak:
Preface. J. Syst. Archit. 49(12-15): 485-487 (2003) - [c35]Lech Józwiak, Szymon Bieganski, Artur Chojnacki:
Information-driven Library-based Circuit Synthesis. DSD 2003: 148-157 - 2002
- [j16]Lech Józwiak, Adam Postula:
Genetic engineering versus natural evolution: Genetic algorithms with deterministic operators. J. Syst. Archit. 48(1-3): 99-112 (2002) - [j15]Marek A. Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Józwiak:
Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach. IEEE Micro 22(3): 41-51 (2002) - [j14]Marek A. Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Józwiak:
Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture. IEEE Micro 22(3): 52-61 (2002) - [j13]Lech Józwiak, Aleksander Slusarczyk, Marek A. Perkowski:
Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits. VLSI Design 14(1): 107-122 (2002) - [c34]Aleksander Slusarczyk, Lech Józwiak:
Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. ISQED 2002: 87-92 - 2001
- [j12]Marek A. Perkowski, Lech Józwiak, William Zhao:
Symbolic two-dimensional minimization of strongly unspecified finite state machines. J. Syst. Archit. 47(1): 15-28 (2001) - [j11]Mariusz Rawski
Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures. J. Syst. Archit. 47(2): 137-155 (2001) - [j10]Lech Józwiak:
Modern methods and tools in digital system design. J. Syst. Archit. 47(3-4): 197-200 (2001) - [j9]Lech Józwiak:
Quality-driven design in the system-on-a-chip era: Why and how? J. Syst. Archit. 47(3-4): 201-224 (2001) - [c33]Lech Józwiak, Artur Chojnacki:
High-quality sub-function construction in functional decomposition based on information relationship measures. DATE 2001: 383-390 - [c32]Lech Józwiak, Artur Chojnacki:
Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. DSD 2001: 30-37 - [c31]Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk:
Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis. DSD 2001: 46-53 - [c30]Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola:
Regular Realization of Symmetric Functions Using Reversible Logic. DSD 2001: 245-253 - [c29]Artur Chojnacki, Lech Józwiak:
High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. ISQED 2001: 409-414 - 2000
- [c28]Lech Józwiak, Aleksander Slusarczyk:
A New State Assignment Method Targeting FPGA Implementations. EUROMICRO 2000: 1050-1059 - [c27]Artur Chojnacki, Lech Józwiak:
Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures. ISMVL 2000: 83-90 - [c26]Lech Józwiak:
Quality-Driven System-on-a-Chip Design. ISQED 2000: 93-
1990 – 1999
- 1999
- [c25]Lech Józwiak:
Digital System Design: Architectures, Methods and Tools. EUROMICRO 1999: 1004- - [c24]Mariusz Rawski
The Influence of the Number of Values in Sub-Functions on the Effectiveness and Efficiency of the Functional Decomposition. EUROMICRO 1999: 1086-1093 - [c23]Mariusz Rawski
Efficient Input Support Selection for Sub-functions in Functional Decomposition Based on Information Relationship Measures. EUROMICRO 1999: 1094-1101 - [c22]Lech Józwiak, Artur Chojnacki:
Functional Decomposition based on Information Relationship Measures Extremely Effective and Efficient for Symmetric Functions. EUROMICRO 1999: 1150-1160 - [c21]Song Chen, Adam Postula, Lech Józwiak:
Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention. EUROMICRO 1999: 1170-1177 - [c20]Torrey Lewis, Marek A. Perkowski, Lech Józwiak:
Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine. EUROMICRO 1999: 1326-1334 - [c19]Rafal Rzechowski, Tadeusz Luba, Lech Józwiak:
Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into Gates. EUROMICRO 1999: 1368-1375 - [c18]Lech Józwiak, Adam Postula:
Genetic Engineering versus Natural Evolution Genetic Algorithms with Deterministic Operators. IC-AI 1999: 58-64 - [c17]Lech Józwiak:
Information Relationships and Measures in Application to Logic Design. ISMVL 1999: 228-235 - 1998
- [c16]Lech Józwiak, Niek Ederveen, Adam Postula:
Solving Synthesis Problems with Genetic Algorithms. EUROMICRO 1998: 10001-10007 - [c15]Mariusz Rawski
Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measure. EUROMICRO 1998: 10008-10015 - [c14]Michael Burns, Marek A. Perkowski, Lech Józwiak:
An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables. EUROMICRO 1998: 10016-10023 - [c13]Adam Postula, Song Chen, Lech Józwiak, David Abramson
Automated Synthesis of Interleaved Memory Systems for Custom Computing Machine. EUROMICRO 1998: 10115-10122 - [c12]Loc Bao Nguen, Marek A. Perkowski, Lech Józwiak:
Design of Self-Synchronized Component FSMs for Self-Timed Systems. EUROMICRO 1998: 10253-10260 - [c11]Mariusz Rawski, Lech Józwiak, Artur Chojnacki:
Application of the Information Measures to Input Support Selection in Functional Decomposition. Rough Sets and Current Trends in Computing 1998: 573-580 - [c10]Lech Józwiak:
Analysis and Synthesis of Information Systems with Information Relationships and Measures. Rough Sets and Current Trends in Computing 1998: 585-588 - 1997
- [c9]Lech Józwiak:
Information Relationships and Measures An Analysis Apparatus for Efficient Information System Synthesis. EUROMICRO 1997: 13-23 - [c8]Sanof Mohamed, Marek A. Perkowski, Lech Józwiak:
Fast Minimization Of Multi-Output Boolean Functions In Sum-Of-Condition-Decoders Structures. EUROMICRO 1997: 31- - [c7]Lech Józwiak:
On the use of term trees for effective and efficient test pattern generation. EUROMICRO 1997: 87-95 - [c6]Sien-An Ong, Kari Tiensyrjä, Lech Józwiak:
Interactive codesign for real-time embedded control systems: task graph generation from SA/VHDL models. EUROMICRO 1997: 172-181 - [c5]Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang:
Decomposition of Multiple-Valued Relations . ISMVL 1997: 13-18 - [c4]Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak:
Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. ISMVL 1997: 287-292 - 1996
- [c3]Lech Józwiak, Sien-An Ong:
Quality-Driven Decision Making Methodology for System-Level Design. EUROMICRO 1996: 8-18 - 1995
- [j8]Lech Józwiak:
General Decomposition and Its Use in Digital Circuit Synthesis. VLSI Design 3(3-4): 225-248 (1995) - [j7]Frank Volf, Lech Józwiak, Mario Stevens:
Division-Based Versus General Decomposition- Based Multiple-Level Logic Synthesis. VLSI Design 3(3-4): 267-287 (1995) - [j6]Lech Józwiak:
Guest Editor's Introduction. VLSI Design 3(3-4): i-iv (1995) - [c2]Lech Józwiak, Frank Wolf:
Efficient decomposition of assigned sequential machines and Boolean functions for PLD implementations. Electronic Technology Directions 1995: 258-266 - 1993
- [j5]Lech Józwiak:
Algorithms and tools for VLSI design. Microprocess. Microprogramming 38(1-5): 705-706 (1993) - 1992
- [j4]Lech Józwiak:
An Efficient Heuristic Method for State Assignment of Large Sequential Machines. J. Circuits Syst. Comput. 2(1): 1-26 (1992) - [j3]Lech Józwiak, Hein Mijland:
On the use of OR-BDDs for test generation. Microprocess. Microprogramming 35(1-5): 159-166 (1992) - 1991
- [j2]Lech Józwiak, J. C. Kolsteren:
An efficient for the sequential general decomposition of sequential machines. Microprocessing and Microprogramming 32(1-5): 657-664 (1991) - 1990
- [j1]Lech Józwiak:
Simultaneous decompositions of sequential machines. Microprocessing and Microprogramming 30(1-5): 305-312 (1990) - [c1]Lech Józwiak:
Efficent suboptimal state assignment for large sequential machines. EURO-DAC 1990: 536-541
Coauthor Index
Felipe M. G. França
aka: Felipe Maia Galvão França
aka: Felipe Maia Galvão França
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-08-05 21:24 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: