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2020 – today
- 2024
- [c44]Hiroshi Miyata, Kazutami Arimoto, Masatoshi Saitoh, Atsushi Hayami, Hisayoshi Mizuno, Yukihiko Shimazu, Tomoyuki Yokogawa:
Distributed Hierarchical AI Architecture for Meta-Described Local Dynamic Maps in Autonomous Driving. IIAI-AAI 2024: 595-600 - 2023
- [c43]Ryugo Tanaka, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto:
Applying Symbolic Model Checking to Node-graph Style Game Scripts with Time Constraints. GCCE 2023: 881-884 - [c42]Tomoya Kubo, Tomoyuki Yokogawa, Kazutami Arimoto, Masaki Hokari, Isao Kayano:
Enhancing the Generalization Performance of Drowsiness Estimation AI in Drivers Using Time-Series Data from FAUs with Limited Datasets. IIAI-AAI-Winter 2023: 165-170 - 2022
- [c41]Kazuma Toyota, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto:
A Visual Modeling Environment for the nuXmv Model Checker Intended for Novice Users. IIAI-AAI 2022: 684-685 - [c40]Kazuki Wayama
, Tomoyuki Yokogawa
Verifying Game Logic in Unreal Engine 5 Blueprint Visual Scripting System Using Model Checking. ASE 2022: 213:1-213:8 - [c39]Yuji Yano, Hisashi Iwamoto, Takuma Yoshimura, Yoshihiro Nishida, Tatsuya Mori, Kiyotaka Komoku, Hidekuni Takao, Kazutami Arimoto:
28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System. VLSI-DAT 2022: 1-4 - 2021
- [c38]Hidekuni Takao, Kazuki Watatani, Kazutami Arimoto:
New Value Creation by Nano-Tactile Sensor Chip Exceeding our Fingertip Discrimination Ability. HCS 2021: 1-36 - [c37]Hiroshi Miyata, Kazutami Arimoto:
Localized Data Transfer System by Vehicles and Cellular Base Station in Local Area. ICC Workshops 2021: 1-6 - 2020
- [j44]Nao Igawa, Tomoyuki Yokogawa, Sousuke Amasaki, Masafumi Kondo, Yoichiro Sato, Kazutami Arimoto:
Symbolic Representation of Time Petri Nets for Efficient Bounded Model Checking. IEICE Trans. Inf. Syst. 103-D(3): 702-705 (2020) - [c36]Hayato Naito, Tomoyuki Yokogawa, Nao Igawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto:
A Node-Style Visual Programming Environment for the nuXmv Model Checker. GCCE 2020: 71-75 - [c35]Tomoki Kobayashi, Tomoyuki Yokogawa, Nao Igawa, Yoichiro Sato, Kimihoro Sugino, Hiroshi Miyata, Satoshi Fujii, Kazutami Arimoto:
A Edge Master Computing for Pineapple Monitoring System with Drone and Data-management. IIAI-AAI 2020: 404-407 - [c34]Nao Igawa, Tomoyuki Yokogawa, Mami Takahashi, Kazutami Arimoto:
Model Checking of Visual Scripts Created by UE4 Blueprints. IIAI-AAI 2020: 512-515
2010 – 2019
- 2019
- [c33]Satoshi Fujii
Radio link design for ITS integrated network using drone. APWCS 2019: 1-4 - [c32]Akira Matsumoto, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto:
Consistency Verification of UML Sequence Diagrams Modeling Wireless Sensor Networks. IIAI-AAI 2019: 458-461 - [c31]Tomoki Kobayashi, Tomoyuki Yokogawa, Nao Igawa, Yoichiro Sato, Satoshi Fujii
A Compact Low Power AI Module Mounted on Drone for Plant Monitor System. IIAI-AAI 2019: 1081-1082 - 2018
- [c30]Nao Igawa, Tomoyuki Yokogawa, Sousuke Amasaki, Kiyotaka Komoku, Yoichiro Sato, Kazutami Arimoto:
Interpolation Based Unbounded Model Checking for Time Petri Nets. GCCE 2018: 619-623 - 2017
- [c29]Kazutami Arimoto, Daichi Yamashita, Nao Igawa, Tomoyuki Yokogawa, Yoichiro Sato, Isao Kayano, Akio Shiratori:
A smart low power R-R-I heartbeat monitor system with contactless UWB sensor. ISOCC 2017: 63-64 - [c28]Salilthip Phuklang, Tomoyuki Yokogawa, Pattara Leelaprute, Kazutami Arimoto:
Tool Support for Consistency Verification of UML Diagrams. PROFES 2017: 606-609 - 2016
- [j43]Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto:
A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(5): 917-928 (2016) - [c27]Daichi Okamoto, Masafumi Kondo, Tomoyuki Yokogawa, Yoshihiro Sejima, Kazutami Arimoto, Yoichiro Sato:
A Serial Booth Multiplier Using Ring Oscillator. CANDAR 2016: 458-461 - [c26]Kiyotaka Komoku, Kazutami Arimoto, Tomoyuki Yokogawa, Hitoshi Yamauchi, Yoichiro Sato, Hidekuni Takao:
3D2 processing architecture - High reliability and low power computing for novel nano tactile sensor array. ISOCC 2016: 199-200 - 2015
- [j42]Tomoyuki Yokogawa, Masafumi Kondo, Hisashi Miyazaki, Sousuke Amasaki, Yoichiro Sato, Kazutami Arimoto:
Bounded model checking of Time Petri Nets using SAT solver. IEICE Electron. Express 12(2): 20141112 (2015) - 2014
- [c25]Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda:
The LSI implementation of a memory based field programmable device for MCU peripherals. DDECS 2014: 183-188 - [c24]Woogeun Rhee, Gangadhar Burra, Kazutami Arimoto, Pieter Harpe, Brian Otis, David Ruffieux:
F5: Low-power radios for sensor networks. ISSCC 2014: 518-519 - 2013
- [j41]Kazuhiro Ueda, Fukashi Morishita
Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. IEEE J. Solid State Circuits 48(11): 2608-2617 (2013) - [c23]Tomoyuki Yokogawa, Sousuke Amasaki, Keisuke Okazaki, Yoichiro Sato, Kazutami Arimoto, Hisashi Miyazaki:
Consistency Verification of UML Diagrams Based on Process Bisimulation. PRDC 2013: 126-127 - 2012
- [c22]Kazutami Arimoto, Sam Kavusi, Kenneth Salisbury:
What's next in robots? ∼Sensing, processing, networking toward human brain and body. ISSCC 2012: 514 - 2011
- [j40]Toru Shimizu, Kazutami Arimoto, Osamu Nishii, Sugako Otani, Hiroyuki Kondo:
Low Power Platform for Embedded Processor LSIs. IEICE Trans. Electron. 94-C(4): 394-400 (2011) - [j39]Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto:
A Scalable Massively Parallel Processor for Real-Time Image Processing. IEEE J. Solid State Circuits 46(10): 2363-2373 (2011) - [c21]Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa
An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller. COOL Chips 2011: 1-3 - [c20]Yushi Moko, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa
Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G. CVPR Workshops 2011: 157-162 - [c19]Toshihiro Hanawa
PEARL and PEACH: A Novel PCI Express Direct Link and Its Implementation. IPDPS Workshops 2011: 871-879 - [c18]Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa
An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. ISSCC 2011: 266-268 - 2010
- [c17]Toshihiro Hanawa
PEARL: Power-Aware, Dependable, and High-Performance Communication Link Using PCI Express. GreenCom/CPSCom 2010: 284-291 - [c16]Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto:
A scalable massively parallel processor for real-time image processing. ISSCC 2010: 334-335 - [c15]Satoshi Shigematsu, Kazutami Arimoto, Christoph Hagleitner:
Fusion of MEMS and circuits. ISSCC 2010: 526-527 - [c14]Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto:
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. SoCC 2010: 519-524
2000 – 2009
- 2009
- [j38]Hiroki Shimano, Fukashi Morishita
On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. IEICE Trans. Electron. 92-C(3): 356-363 (2009) - [j37]Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto:
A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. IEICE Trans. Electron. 92-C(4): 453-459 (2009) - [j36]Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu:
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. IEEE J. Solid State Circuits 44(8): 2251-2259 (2009) - 2008
- [j35]Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. 91-C(9): 1409-1418 (2008) - [j34]Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto:
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. IEEE J. Solid State Circuits 43(4): 892-901 (2008) - [c13]Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu:
Heterogeneous multicore SoC for secure multimedia applications. CICC 2008: 675-678 - 2007
- [j33]Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. 90-D(1): 334-345 (2007) - [j32]Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu:
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. IEICE Trans. Electron. 90-C(4): 657-665 (2007) - [j31]Fukashi Morishita
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Trans. Electron. 90-C(4): 765-771 (2007) - [j30]Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. 90-D(8): 1312-1315 (2007) - [j29]Hiroki Shimano, Fukashi Morishita
A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. IEICE Trans. Electron. 90-C(10): 1927-1935 (2007) - [j28]Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu:
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits 42(1): 183-192 (2007) - [j27]Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto:
The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits 42(4): 804-812 (2007) - [j26]Fukashi Morishita
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. IEEE J. Solid State Circuits 42(4): 853-861 (2007) - [j25]Kazutami Arimoto, Fukashi Morishita
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. IEEE J. Solid State Circuits 42(11): 2611-2619 (2007) - [c12]Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS 2007: 525-528 - [c11]Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto:
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43 - [c10]Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto:
A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. ISSCC 2007: 490-491 - 2006
- [j24]Takayuki Gyohten, Fukashi Morishita
An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. IEICE Trans. Electron. 89-C(11): 1519-1525 (2006) - [j23]Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. 89-C(11): 1612-1619 (2006) - [c9]Kazutami Arimoto, Fukashi Morishita
A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. CICC 2006: 429-432 - [c8]Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu:
A 40GOPS 250mW massively parallel processor based on matrix architecture. ISSCC 2006: 1616-1625 - 2005
- [j22]Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara:
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. 88-C(4): 622-629 (2005) - [j21]Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide:
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. 88-C(6): 1332-1342 (2005) - [j20]Akira Yamazaki, Fukashi Morishita
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. 88-C(10): 2020-2027 (2005) - [j19]Fukashi Morishita
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits 40(1): 204-212 (2005) - [j18]Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40(1): 245-253 (2005) - [j17]Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. IEEE J. Solid State Circuits 40(11): 2296-2304 (2005) - [c7]Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto:
A capacitorless twin-transistor random access memory (TTRAM) on SOI. CICC 2005: 435-438 - [c6]Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto:
A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. CICC 2005: 451-454 - [c5]Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito:
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) 2005: 5202-5205 - 2003
- [j16]Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki:
A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2991-3000 (2003) - [j15]Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto:
An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. IEEE J. Solid State Circuits 38(11): 1967-1973 (2003) - 2001
- [j14]Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara:
Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits 36(1): 46-54 (2001) - [c4]Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada:
Test cost reduction by at-speed BISR for embedded DRAMs. ITC 2001: 182-187 - 2000
- [j13]Tadaaki Yamauchi, Fukashi Morishita
High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits 35(8): 1169-1178 (2000)
1990 – 1999
- 1999
- [j12]Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima
A 5.3-GB/s embedded SDRAM core with slight-boost scheme. IEEE J. Solid State Circuits 34(5): 661-669 (1999) - 1998
- [j11]Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada:
400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits 33(5): 770-778 (1998) - 1997
- [j10]Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada:
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. IEEE J. Solid State Circuits 32(3): 477-482 (1997) - [j9]Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma:
A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. IEEE J. Solid State Circuits 32(11): 1712-1720 (1997) - [j8]Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto:
A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. IEEE J. Solid State Circuits 32(11): 1721-1727 (1997) - 1996
- [j7]Shigehiro Kuge, Fukashi Morishita
SOI-DRAM circuit technologies for low power high speed multigiga scale memories. IEEE J. Solid State Circuits 31(4): 586-591 (1996) - [j6]Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe:
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. IEEE J. Solid State Circuits 31(11): 1645-1655 (1996) - 1995
- [j5]Tadato Yamagata, Shigeki Tomishima
Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. IEEE J. Solid State Circuits 30(11): 1183-1188 (1995) - 1994
- [j4]Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. IEEE J. Solid State Circuits 29(4): 432-440 (1994) - 1993
- [j3]Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima:
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. 10(2): 6-12 (1993) - 1992
- [c3]Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima:
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC 1992: 615-622
1980 – 1989
- 1989
- [j2]Kiyohiro Furutani, Kazutami Arimoto, Hiroshi Miyamoto, Toshifumi Kobayashi, Kenichi Yasuda, Koichiro Mashiko:
A built-in Hamming code ECC circuit for DRAMs. IEEE J. Solid State Circuits 24(1): 50-56 (1989) - [j1]Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano:
A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. IEEE J. Solid State Circuits 24(5): 1184-1190 (1989) - [c2]Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima:
A New Array Architecture for Parallel Testing in VLSI Memories. ITC 1989: 322-326 - 1985
- [c1]Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, Takao Nakano:
Test Pattern Considerations for Fault Tolerant High Density DRAM. ITC 1985: 451-455
Coauthor Index
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