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39th DAC 2002: New Orleans, LA, USA
- Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002. ACM 2002, ISBN 1-58113-461-4
Wall street evaluates EDA
- Moshe Gavrielov, Richard Goering, Lucio Lanza, Vishal Saluja, Jay Vleeschhouwer:
Wall street evaluates EDA. 1
Web and IP based design
- Michael J. Wirthlin, Brian McMurtrey:
IP delivery for FPGAs using Applets and JHDL. 2-7 - Seapahn Megerian, Milenko Drinic, Miodrag Potkonjak:
Watermarking integer linear programming solutions. 8-13 - Fabrice Bernardi, Jean François Santucci:
Model design using hierarchical web-based libraries. 14-17 - Milenko Drinic, Darko Kirovski:
Behavioral synthesis via engineering change. 18-21
Design innovations for embedded processors
- Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann:
A universal technique for fast and flexible instruction-set architecture simulation. 22-27 - Roman L. Lysecky, Susan Cotterell, Frank Vahid:
A fast on-chip profiler memory. 28-33 - Haris Lekatsas, Jörg Henkel, Venkata Jakkula:
Design of an one-cycle decompression hardware for performance increase in embedded systems. 34-39
Passive model order reduction
- Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh:
A factorization-based framework for passivity-preserving model reduction of RLC systems. 40-45 - Luca Daniel, Joel R. Phillips:
Model order reduction for strictly passive and causal distributed systems. 46-51 - Joel R. Phillips, Luca Daniel, Luís Miguel Silveira:
Guaranteed passive balancing transformations for model order reduction. 52-57
New perspectives in physical design
- Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski:
Uncertainty-aware circuit optimization. 58-63 - Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif:
Congestion-driven codesign of power and signal networks. 64-69 - PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
On metrics for comparing routability estimation methods for FPGAs. 70-75
Panel: Tools or Users: Which is the Bigger Bottleneck?
- Andrew B. Kahng, Ronald Collett, Patrick Groeneveld, Lavi Lev, Nancy Nettleton, Paul K. Rodman, Lambert van den Hoven:
Tools or users: which is the bigger bottleneck? 76-77
Life after CMOS: Imminent or Irrelevant?
- George Sery, Shekhar Borkar, Vivek De:
Life is CMOS: why chase the life after? 78-83 - H. Bernhard Pogge:
The next chip challenge: effective methods for viable mixed technology SoCs. 84-87 - Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier:
Few electron devices: towards hybrid CMOS-SET integrated circuits. 88-93 - Richard Martel, V. Derycke, Jörg Appenzeller, Shalom J. Wind, Phaedon Avouris
:
Carbon nanotube field-effect transistors and logic circuits. 94-98
Formal verification
- Valeria Bertacco, Kunle Olukotun:
Efficient state representation for symbolic simulation. 99-104 - Alfred Kölbl, James H. Kukula, Kurt Antreich, Robert F. Damiano:
Handling special constructs in symbolic simulation. 105-110 - Scott Hazelhurst, Osnat Weissberg, Gila Kamhi, Limor Fix:
A hybrid verification approach: getting deep into the design. 111-116 - Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Can BDDs compete with SAT solvers on bounded model checking? 117-122
High level specification and design
- Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng:
RTL c-based methodology for designing and verifying a multi-threaded processor. 123-128 - Marcio T. Oliveira, Alan J. Hu:
High-Level specification and automatic generation of IP interface monitors. 129-134 - Kerstin Eder, Geoff Barrett:
Achieving maximum performance: a method for the verification of interlocked pipeline control logic. 135-140 - Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee:
Formal verification of module interfaces against real time specifications. 141-145
Timing abstraction
- Ajay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, Qiuyang Wu:
Automated timing model generation. 146-151 - Cho W. Moon, Harish Kriplani, Krishna P. Belkhale:
Timing model extraction of hierarchical blocks by graph reduction. 152-157 - Martin Foltin, Brian Foutz, Sean Tyler:
Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency. 158-163 - Hiroyuki Higuchi:
An implication-based method to detect multi-cycle paths in large sequential circuits. 164-169
E-textiles
- Sungmee Park, Kenneth Mackenzie, Sundaresan Jayaraman:
The wearable motherboard: a framework for personalized mobile information processing (PMIP). 170-174 - Diana Marculescu
Challenges and opportunities in electronic textiles modeling and optimization. 175-180
Panel: Analog Intellectual Property: Now? Or Never?
- Mike Brunoli, Masao Hotta, Felicia James, Rudy Koch, Roy McGuffin, Andrew J. Moore:
Analog intellectual property: now? Or never? 181-182
Low-power system design
- Yumin Zhang, Xiaobo Hu, Danny Z. Chen:
Task scheduling and voltage selection for energy minimization. 183-188 - Daler N. Rakhmatov, Sarma B. K. Vrudhula, Chaitali Chakrabarti:
Battery-conscious task sequencing for portable devices including voltage/clock scaling. 189-194 - Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karaköy:
An energy saving strategy based on adaptive loop parallelization. 195-200
Fabric-driven logic synthesis
- Fan Mo, Robert K. Brayton:
River PLAs: a regular circuit structure. 201-206 - Junhyung Um, Taewhan Kim:
Layout-aware synthesis of arithmetic circuits. 207-212
Memory management and address optimization in embedded systems
- Victor De La Luz, Mahmut T. Kandemir, Ibrahim Kolcu:
Automatic data migration for reducing energy consumption in multi-bank memory systems. 213-218 - Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary:
Exploiting shared scratch pad memory space in embedded multiprocessor systems. 219-224 - Yoonseo Choi, Taewhan Kim:
Address assignment combined with scheduling in DSP code generation. 225-230
Optics: lighting the way to EDA riches?
- Edward H. Sargent:
Multifunctional photonic integration for the agile optical internet. 231-234 - James G. Maloney, Brian E. Brewington, Curtis R. Menyuk:
Computer aided design of long-haul optical transmission systems. 235 - Timothy P. Kurzweg, Steven P. Levitan, Jose A. Martinez, Mark Kahrs, Donald M. Chiarulli:
A fast optical propagation technique for modeling micro-optical systems. 236-241
PANEL: Nanometer Design: What Hurts Next...?
- Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi:
Nanometer design: what hurts next...? 242
Novel DFT, BIST and diagnosis techniques
- Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick:
Low-cost sequential ATPG with clock-control DFT. 243-248 - Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston:
Effective diagnostics through interval unloads in a BIST environment. 249-254 - Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy:
On output response compression in the presence of unknown output values. 255-258 - Li Chen, Sujit Dey:
Software-based diagnosis for processors. 259-262
Case studies in embedded system design
- Xun Liu, Marios C. Papaefthymiou:
Design of a high-throughput low-power IS95 Viterbi decoder. 263-268 - Daniel Ragan, Peter Sandborn, Paul Stoaks:
A detailed cost model for concurrent use with hardware/software co-design. 269-274 - Hyunok Oh, Soonhoi Ha:
Efficient code synthesis from extended dataflow graphs for multimedia applications. 275-280
Theoretical foundations of embedded system design
- Ingo Sander, Axel Jantsch:
Transformation based communication and clock domain refinement for system design. 281-286 - Kai Richter, Dirk Ziegenbein, Marek Jersak, Rolf Ernst:
Model composition for scheduling analysis in platform design. 287-292 - Jong-Yeol Lee, In-Cheol Park
Timed compiled-code simulation of embedded software for performance analysis of SOC design. 293-298
Equivalence verification
- Simon Jolly, Atanas N. Parashkevov, Tim McDougall:
Automated equivalence checking of switch level circuits . 299-304 - Demos Anastasakis, Robert F. Damiano, Hi-Keung Tony Ma, Ted Stanion:
A practical and efficient method for compare-point matching. 305-310 - Ying-Tsai Chang, Kwang-Ting Cheng:
Self-referential verification of gate-level implementations of arithmetic circuits. 311-316
PANEL: Whither (or Wither?) ASIC Handoff
- Michael Santarini, Sudhakar Jilla, Mark Miller, Tommy Eng, Sandeep Khanna, Kamalesh N. Ruparel, Tom Russell, Kazu Yamada:
Whither (or wither?) ASIC handoff? 317-318
Embedded software automation: from specification to binary
- Yunjian Jiang, Robert K. Brayton:
Software synthesis from synchronous specifications using logic simulation techniques. 319-324 - Armita Peymandoust, Giovanni De Micheli, Tajana Simunic:
Complex library mapping for embedded software using symbolic algebra. 325-330 - Maghsoud Abbaspour, Jianwen Zhu:
Retargetable binary utilities. 331-336
Applications of reconfigurable computing
- Zhining Huang, Sharad Malik
Exploiting operation level parallelism through dynamically reconfigurable datapaths. 337-342 - Edson L. Horta, John W. Lockwood, David E. Taylor, David B. Parlour:
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. 343-348 - Jinghuan Chen, Jaekyun Moon, Kia Bazargan:
A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator. 349-354
New test methods targeting non-classical faults
- Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey:
Embedded software-based self-testing for SoC design. 355-360 - Swarup Bhunia, Kaushik Roy, Jaume Segura:
A novel wavelet transform based transient current analysis for fault detection and localization. 361-366 - Amir Attarha, Mehrdad Nourani:
Signal integrity fault analysis using reduced-order modeling. 367-370 - Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes. 371-374
How Do You Design a 10M Gate ASIC?
- Christian Berthet:
Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry. 375-378
Power distribution issues
- Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, Charlie Chung-Ping Chen:
HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery. 379-384 - Srinivas Bodapati, Farid N. Najm:
High-level current macro-model for power-grid analysis. 385-390 - Brian W. Amick, Claude R. Gauthier, Dean Liu:
Macro-modeling concepts for the chip electrical interface. 391-394 - Hui Zheng, Lawrence T. Pileggi:
Modeling and analysis of regular symmetrically structured power/ground distribution networks. 395-398 - Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen:
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. 399-404
Advances in synthesis
- Tiberiu Chelcea, Steven M. Nowick:
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. 405-410 - Alex Kondratyev, Kelvin Lwin:
Design of asynchronous circuits by synchronous CAD tools. 411-414 - Christos P. Sotiriou:
Implementing asynchronous circuits using a conventional EDA tool-flow. 415-418 - Kazuo Iwama, Yahiko Kambayashi, Shigeru Yamashita:
Transformation rules for designing CNOT-based quantum circuits. 419-424 - Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Fast three-level logic minimization based on autosymmetry. 425-430
Analog synthesis & design methodology
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits. 431-436 - Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley:
Remembrance of circuits past: macromodeling by data mining in large analog design spaces. 437-442 - Ovidiu Bajdechi, Johan H. Huijsing, Georges G. E. Gielen:
Optimal design of delta-sigma ADCs by design space exploration. 443-448 - Jan Vandenbussche, Koen Uyttenhove, Erik Lauwers, Michiel Steyaert, Georges G. E. Gielen:
Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter. 449-454
Low-power physical design
- Ashok K. Murugavel, N. Ranganathan:
Petri net modeling of gate and interconnect delays for power estimation. 455-460 - Pawan Kapur, Gaurav Chandra, Krishna Saraswat:
Power estimation in global interconnects and its reduction using a novel repeater optimization methodology. 461-466 - Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Low-swing clock domino logic incorporating dual supply and dual threshold voltages. 467-472 - Amit Agarwal, Hai Li, Kaushik Roy:
DRG-cache: a data retention gated-ground cache for low power. 473-478
PANEL: Unified Tools for SoC Embedded Systems: Mission Critical, Mission Impossible or Mission Irrelevant?
- Gary Smith, Daya Nadamuni, Sharad Malik
Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? 479
Multi-voltage, multi-threshold design
- Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, Shawki Areibi:
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. 480-485 - Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar:
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. 486-491 - Dong-In Kang, Jinwoo Suh, Stephen P. Crago:
An optimal voltage synthesis technique for a power-efficient satellite application. 492-497
Advanced simulation techniques
- Michael H. Perrott:
Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits. 498-503 - Baolin Yang, Joel R. Phillips:
Time-domain steady-state simulation of frequency-dependent components using multi-interval Chebyshev method. 504-509 - Jaijeet S. Roychowdhury:
A time-domain RF steady-state method for closely spaced tones. 510-513 - Giorgio Casinovi:
An algorithm for frequency-domain noise analysis in nonlinear systems. 514-517
Design methodologies meet network applications
- Chantal Ykman-Couvreur, Jurgen Lambrecht, Diederik Verkest, Francky Catthoor, Aristides Nikologiannis, George E. Konstantoulakis:
System-level performance optimization of the data queueing memory management in high-speed network processors. 518-523 - Terry Tao Ye
Analysis of power consumption on switch fabrics in network routers. 524-529 - David Whelihan, Herman Schmit:
Memory optimization in single chip network switch fabrics. 530-535
Advances in analog modeling
- Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Behavioral modeling of (coupled) harmonic oscillators. 536-541 - Walter Hartong, Lars Hedrich, Erich Barke:
Model checking algorithms for analog verification. 542-547 - Jochen Mades, Manfred Glesner:
Regularization of hierarchical VHDL-AMS models using bipartite graphs. 548-551 - Yehia Massoud, Jacob White:
Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materials. 552-555
Advances in timing and simulation
- Michael Orshansky, Kurt Keutzer:
A general probabilistic framework for worst case timing analysis. 556-561 - Jing Zeng, Magdy S. Abadir, Jacob A. Abraham:
False timing path identification using ATPG techniques and delay-based information. 562-565 - Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng:
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. 566-569 - Srihari Cadambi, Chandra Mulpuri, Pranav Ashar:
A fast, inexpensive and scalable hardware acceleration technique for functional simulation. 570-575
Formal Verification Methods: Getting around the Brick Wall
- David L. Dill, Nate James, Shishpal Rawat, Gérard Berry, Limor Fix, Harry Foster, Rajeev K. Ranjan, Gunnar Stålmarck, Curt Widdoes:
Formal verification methods: getting around the brick wall. 576-577
Routing and buffering
- Milos Hrkic, John Lillis:
S-Tree: a technique for buffered routing tree synthesis. 578-583 - Hua Xiang, D. F. Wong
An algorithm for integrated pin assignment and buffer planning. 584-589 - Narendra V. Shenoy, William Nicholls:
An efficient routing database. 590-595
System on chip design
- Ferid Gharsalli, Samy Meftali, Frédéric Rousseau, Ahmed Amine Jerraya:
Automatic generation of embedded memory wrapper for multiprocessor SoC. 596-601 - Robert Siegmund, Dietmar Müller:
A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications. 602-607 - Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda:
An integrated algorithm for memory allocation and assignment in high-level synthesis. 608-611 - María C. Molina, José M. Mendías, Román Hermida:
High-level synthesis of multiple-precision circuitsindependent of data-objects length. 612-615
Timing analysis and memory optimization for embedded systems
- Samarjit Chakraborty, Thomas Erlebach, Simon Künzli, Lothar Thiele:
Schedulability of event-driven code blocks in real-time embedded systems. 616-621 - Fabian Wolf, Jan Staschulat, Rolf Ernst:
Associative caches in formal software timing analysis. 622-627 - Mahmut T. Kandemir, Alok N. Choudhary:
Compiler-directed scratch pad memory hierarchy design and management. 628-633
Processors and accelerators for embedded applications
- Patrick Schaumont
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor. 634-639 - Nick Richardson, Lun Bin Huang, Razak Hossain, Tommy Zounes, Naresh Soni, Julian Lewis:
The iCOREtm 520 MHz synthesizable CPU core. 640-645 - Gokhan Memik, William H. Mangione-Smith:
A flexible accelerator for layer 7 networking applications. 646-651
PANEL: What's the Next EDA Driver?
- Jan M. Rabaey, Joachim Kunkel, Dennis Brophy, Raul Camposano, Davoud Samani, Larry Lerner, Rick Hetherington:
What's the next EDA driver? 652
Cross-talk noise analysis and management
- Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul:
Estimation of the likelihood of capacitive coupling noise. 653-658 - Paul B. Morton, Wayne Wei-Ming Dai:
Crosstalk noise estimation for noise management. 659-664 - Byron Krauter, David Widiger:
Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmax. 665-668 - James D. Z. Ma, Lei He:
Towards global routing with RLC crosstalk constraints. 669-672
Test cost reduction for SOCS
- Anshuman Chandra, Krishnendu Chakrabarty
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. 673-678 - Douglas Kay, Sung Chung, Samiha Mourad:
Embedded test control schemes for compression in SOCs. 679-684 - Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. 685-690
Scheduling techniques for embedded systems
- Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Communication architecture based power management for battery efficient system design. 691-696 - Victor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Scheduler-based DRAM energy management. 697-702 - Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer:
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors. 703-708
Designing SoCs for yield improvement
- Yervant Zorian:
Embedding infrastructure IP for SOC yield improvement. 709-712 - Miron Abramovici, Charles E. Stroud, John Marty Emmert:
Using embedded FPGAs for SoC yield improvement. 713-724
Advances in SAT
- Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna:
A proof engine approach to solving combinational design automation problems. 725-730 - Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Solving difficult SAT instances in the presence of symmetry. 731-736 - Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah:
Satometer: how much have we searched? 737-742 - Slawomir Pilarski, Gracia Hu:
SAT with partial clauses and back-leaps. 743-746 - Malay K. Ganai, Pranav Ashar, Aarti Gupta
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. 747-750
Inductance and substrate analysis
- Hemant Mahawar, Vivek Sarin, Weiping Shi:
A solenoidal basis method for efficient inductance extraction. 751-756 - Tao Lin, Michael W. Beattie, Lawrence T. Pileggi:
On the efficacy of simplified 2D on-chip inductance models. 757-762 - Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl:
A physical model for the transient response of capacitively loaded distributed rlc interconnects. 763-766 - Adil Koukab, Catherine Dehollain, Michel J. Declercq:
HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC. 767-770 - Eelco Schrik, N. P. van der Meijs:
Combined BEM/FEM substrate resistance modeling. 771-776
Development of processors and communication networks for embedded systems
- Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass:
System design methodologies for a wireless security processing platform. 777-782 - Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
Constraint-driven communication synthesis. 783-788 - Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava:
Component-based design approach for multicore SoCs. 789-794 - Girish Varatkar, Radu Marculescu:
Traffic analysis for on-chip networks design of multimedia applications. 795-800
Moving towards more effective validation
- Kanna Shimizu, David L. Dill:
Deriving a simulation input generator and a coverage metric from a formal specification. 801-806 - Oded Lachish, Eitan Marcus, Shmuel Ur, Avi Ziv:
Hole analysis for functional coverage data. 807-812 - Shuo Sheng, Koichiro Takayama, Michael S. Hsiao:
Effective safety property checking using simulation-based sequential ATPG. 813-818 - Mike Bartley, Darren Galpin, Tim Blackmore:
A comparison of three verification techniques: directed testing, pseudo-random testing and property checking. 819-823
Energy efficient mobile computing
- Carla-Fabiana Chiasserini, Pavan Nuggehalli, Vikram Srinivasan:
Energy-efficient communication protocols. 824-829 - Naresh R. Shanbhag:
Reliable and energy-efficient digital signal processing. 830-835 - Michiel Steyaert, Peter J. Vancorenland:
CMOS: a paradigm for low power wireless? 836-841
Floorplanning and placement
- Jai-Ming Lin, Yao-Wen Chang:
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. 842-847 - Xiaoping Tang, D. F. Wong
Floorplanning with alignment and performance constraints. 848-853 - Ke Zhong, Shantanu Dutt:
Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control. 854-859
Circuit effects in static timing
- Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer
Coping with buffer delay change due to power and ground noise. 860-865 - Bernard N. Sheehan:
Osculating Thevenin model for predicting delay and slew of capacitively characterized cells. 866-869 - Seung Hoon Choi, Kaushik Roy, Florentin Dartu:
Timed pattern generation for noise-on-delay calculation. 870-873 - Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang:
VeriCDF: a new verification methodology for charged device failures. 874-879
Design space exploration for embedded systems
- Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Künzli:
A framework for evaluating design tradeoffs in packet processing architectures. 880-885 - Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon:
Energy estimation and optimization of embedded VLIW processors based on instruction clustering. 886-891 - Yongsoo Joo
Energy exploration and reduction of SDRAM memory systems. 892-897
Behavioral synthesis
- Sumit Gupta, Nick Savoiu, Nikil D. Dutt
Coordinated transformations for high-level synthesis of high performance microprocessor blocks. 898-903 - Jennifer L. Wong
Forward-looking objective functions: concept & applications in high level synthesis. 904-909 - Farinaz Koushanfar
ILP-based engineering change. 910-915
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