Article

Life is CMOS: why chase the life after?

Authors:

George Sery,

Shekhar Borkar,

Vivek DeAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 78 - 83

https://doi.org/10.1145/513918.513941

Published: 10 June 2002 Publication History

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Abstract

This paper discusses potential solutions to the CMOS device technology scaling at gate lengths approaching 10nm. Promising circuit and design techniques to control leakage power are described. Energy-efficient microarchitecture trends for general-purpose microprocessors are elucidated.

References

[1]

R. Chau et al., "30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays", IEDM 2000, pp. 45--48.

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[2]

R. Chau, "30nm and 20nm Physical Gate Length CMOS Transistors", Silicon Nanotechnology Workshop, 2001.

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[3]

R. Chau et al., "A 50nm depleted-substrate CMOS transistor (DST)", IEDM 2001, pp. 621--624.

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[4]

Fred Pollack; New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies; Micro32, 1999.

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Aggarwal RJiang LPatra SLajo NKabir EKasim R(2022)A Novel Approach for Assessing Impact of Temperature Hot-Spots on Chip-Package Interaction Reliability2022 IEEE International Reliability Physics Symposium (IRPS)10.1109/IRPS48227.2022.9764409(4C.4-1-4C.4-5)Online publication date: Mar-2022
https://doi.org/10.1109/IRPS48227.2022.9764409
Singh DPandey NGupta K(2022)A novel read decoupled 8T1M nvSRAM cell with improved read/write marginAnalog Integrated Circuits and Signal Processing10.1007/s10470-022-02121-z114:1(89-101)Online publication date: 28-Dec-2022
https://doi.org/10.1007/s10470-022-02121-z
Gupta MGupta KPandey N(2021)Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nmMicroprocessors and Microsystems10.1016/j.micpro.2021.10428185(104281)Online publication date: Sep-2021
https://doi.org/10.1016/j.micpro.2021.104281
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Index Terms

Life is CMOS: why chase the life after?
1. Hardware
  1. Integrated circuits
  2. Very large scale integration design

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Published In

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 10 June 2002

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DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Aggarwal RJiang LPatra SLajo NKabir EKasim R(2022)A Novel Approach for Assessing Impact of Temperature Hot-Spots on Chip-Package Interaction Reliability2022 IEEE International Reliability Physics Symposium (IRPS)10.1109/IRPS48227.2022.9764409(4C.4-1-4C.4-5)Online publication date: Mar-2022
https://doi.org/10.1109/IRPS48227.2022.9764409
Singh DPandey NGupta K(2022)A novel read decoupled 8T1M nvSRAM cell with improved read/write marginAnalog Integrated Circuits and Signal Processing10.1007/s10470-022-02121-z114:1(89-101)Online publication date: 28-Dec-2022
https://doi.org/10.1007/s10470-022-02121-z
Gupta MGupta KPandey N(2021)Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nmMicroprocessors and Microsystems10.1016/j.micpro.2021.10428185(104281)Online publication date: Sep-2021
https://doi.org/10.1016/j.micpro.2021.104281
Roy CIslam A(2018)Design of differential TG based 8T SRAM cell for ultralow-power applicationsMicrosystem Technologies10.1007/s00542-018-4035-7Online publication date: 19-Jul-2018
https://doi.org/10.1007/s00542-018-4035-7
Verma PSharma ANoor APandey V(2017)SDTSPC-technique for low power noise aware 1-bit full adderAnalog Integrated Circuits and Signal Processing10.1007/s10470-017-0994-392:2(303-314)Online publication date: 1-Aug-2017
https://dl.acm.org/doi/10.1007/s10470-017-0994-3
Kanduri ARahmani ALiljeberg PHemani AJantsch ATenhunen H(2017)A Perspective on Dark SiliconThe Dark Side of Silicon10.1007/978-3-319-31596-6_1(3-20)Online publication date: 1-Jan-2017
https://doi.org/10.1007/978-3-319-31596-6_1
Verma PNoor ASharma ASampath Kumar V. (2016)Power gating and its repercussions—a review2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES)10.1109/ICPEICES.2016.7853208(1-6)Online publication date: Jul-2016
https://doi.org/10.1109/ICPEICES.2016.7853208
Samandari-Rad JHughey R(2016)Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAMIEEE Access10.1109/ACCESS.2016.25213854(594-613)Online publication date: 2016
https://doi.org/10.1109/ACCESS.2016.2521385
Lin JLin C(2015)Placement Density Aware Power Switch Planning Methodology for Power Gating DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.240157334:5(766-777)Online publication date: May-2015
https://doi.org/10.1109/TCAD.2015.2401573
Lin JLin CSyu ZTsai CHuang KSze CDavoodi A(2014)Current density aware power switch placement algorithm for power gating designsProceedings of the 2014 on International symposium on physical design10.1145/2560519.2560527(85-92)Online publication date: 30-Mar-2014
https://dl.acm.org/doi/10.1145/2560519.2560527
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Abstract

References

Cited By

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Recommendations

Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile

Gate leakage reduction for scaled devices using transistor stacking

Predictive technology model for nano-CMOS design exploration

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