Article

Petri net modeling of gate and interconnect delays for power estimation

Authors:

Ashok K. Murugavel,

N. RanganathanAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 455 - 460

https://doi.org/10.1145/513918.514034

Published: 10 June 2002 Publication History

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Abstract

In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit is converted into a HCHPN and simulated as a Petri net to get the switching activity estimate and thus the power values. The method is accurate and is significantly faster than other simulative methods. The HCHPN yields an average error of 4.9% with respect to Hspice for the ISCAS '85 benchmark circuits. The per-pattern simulation time is about 46 times lesser than PowerMill.

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Cited By

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Junior MNeto SMaciel PLima RRibeiro ABarreto RTavares EBraga F(2006)Analyzing software performance and energy consumption of embedded systems by probabilistic modelingProceedings of the 27th international conference on Applications and Theory of Petri Nets and Other Models of Concurrency10.1007/11767589_15(261-281)Online publication date: 26-Jun-2006
https://dl.acm.org/doi/10.1007/11767589_15
Junior MMaciel PLima RRibeiro AOliveira CArcoverde ABarreto RTavares EAmorin L(2005)A retargetable environment for power-aware code evaluationProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_6(49-58)Online publication date: 21-Sep-2005
https://dl.acm.org/doi/10.1007/11556930_6
Tang FLi MHuang JWang CLuo Z(2004)Petri-Net-Based coordination algorithms for grid transactionsProceedings of the Second international conference on Parallel and Distributed Processing and Applications10.1007/978-3-540-30566-8_60(499-508)Online publication date: 13-Dec-2004
https://dl.acm.org/doi/10.1007/978-3-540-30566-8_60
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Index Terms

Petri net modeling of gate and interconnect delays for power estimation
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation
  2. Integrated circuits

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Information

Published In

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 10 June 2002

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DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Junior MNeto SMaciel PLima RRibeiro ABarreto RTavares EBraga F(2006)Analyzing software performance and energy consumption of embedded systems by probabilistic modelingProceedings of the 27th international conference on Applications and Theory of Petri Nets and Other Models of Concurrency10.1007/11767589_15(261-281)Online publication date: 26-Jun-2006
https://dl.acm.org/doi/10.1007/11767589_15
Junior MMaciel PLima RRibeiro AOliveira CArcoverde ABarreto RTavares EAmorin L(2005)A retargetable environment for power-aware code evaluationProceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11556930_6(49-58)Online publication date: 21-Sep-2005
https://dl.acm.org/doi/10.1007/11556930_6
Tang FLi MHuang JWang CLuo Z(2004)Petri-Net-Based coordination algorithms for grid transactionsProceedings of the Second international conference on Parallel and Distributed Processing and Applications10.1007/978-3-540-30566-8_60(499-508)Online publication date: 13-Dec-2004
https://dl.acm.org/doi/10.1007/978-3-540-30566-8_60
Murugavel ARanganathan N(2003)Petri net modeling of gate and interconnect delays for power estimationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81711011:5(921-927)Online publication date: 1-Oct-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.817110

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