Article

Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency

Authors:

Martin Foltin,

Brian Foutz,

Sean TylerAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 158 - 163

https://doi.org/10.1145/513918.513958

Published: 10 June 2002 Publication History

Get Access

Abstract

We have developed a new timing abstraction model for digital circuit blocks that is stimulus independent, port based, supports designs with level triggered latches, and can be input into commercial STA (Static Timing Analysis) tools. The model is based on an extension of the concept of latch transparency to circuit block transparency introduced in this paper. It was implemented, tested and is being used in conjunction with transistor level STA for microprocessor designs with tens of millions of transistors. The STA simulation times are significantly shorter than with gray box timing models, which can decrease the overall chip timing verification time. The model can also be used in the intellectual property encapsulation domain.

References

[1]

Hitchcock, R.B., Sr., Smith, G.L., Cheng, D.D., Timing analysis of computer hardware, IBM J. Res. Develop. 26 (1982) 100--105

Digital Library

Google Scholar

[2]

McDonald, C., Indermaur, T., Buckley, M., Timing analysis for the PA-8000, Integrated System Design (isdmag.com), February 1997, Cover Story

Google Scholar

[3]

Avidan, J., Circuit analyzer of black, gray and transparent elements, U.S. Patent No. 6158022

Google Scholar

[4]

Segal, R.B., Extracting accurate and efficient timing models of latch-based designs, U.S. Patent No. 6023568

Google Scholar

[5]

Venkatesh, S.V., Palermo, R., Mortazavi, M., Sakallah, K.A., Timing abstraction of intellectual property blocks, IEEE 1997 Custom Integrated Circuits Conference, 99--102

Google Scholar

[6]

Burks, T.M., Sakallah, K.A., Mudge, T.N., Critical paths in circuits with level-sensitive latches, IEEE Trans. on VLSI systems, 3 (1995) 273--291

Digital Library

Google Scholar

[7]

PathMillPlus, Synopsys Products and Solutions Web page http://www.synopsys.com/products/analysis/pathmillplus_ds.html

Google Scholar

Cited By

View all

Do KKim YSon H(2007)Timing modeling of latch-controlled sub-systemsIntegration10.1016/j.vlsi.2006.02.00740:2(62-73)Online publication date: Feb-2007
https://doi.org/10.1016/j.vlsi.2006.02.007
Chen RZhou H(2004)Timing macro-modeling of IP blocks with crosstalkProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382563(155-159)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382563
Lin CZhou H(2003)Retiming for Wire Pipelining in System-On-ChipProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009893Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009893

Index Terms

Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency
1. Hardware
  1. Hardware validation
    1. Functional verification

Recommendations

Robust Optimization of Multiple Timing Constraints
Modern field-programmable gate array (FPGA) circuit designs often contain multiple clocks and complex timing constraints, and achieving these constraints requires timing optimization at all stages of the computer-aided design (CAD) flow. To our knowledge, ...
The Jitter Model for Metastability and its Application to Redundant Synchronizers

A synchronizer timing model, called the jitter model, which has general application to metastable reliability analysis, is proposed and analyzed. The jitter model is applied to show that redundancy cannot improve the metastable reliability of ...
Fast timing-model independent buffered clock-tree synthesis
DAC '10: Proceedings of the 47th Design Automation Conference

In high-performance synchronous chip design, a buffered clock tree with small clock skew is essential for improving clocking speed. Due to the insufficient accuracy of timing models for modern chip design, embedding simulation into a clock-tree ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 June 2002

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC02

Sponsor:

SIGDA

DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

Acceptance Rates

DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
13
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)1

Reflects downloads up to 21 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Do KKim YSon H(2007)Timing modeling of latch-controlled sub-systemsIntegration10.1016/j.vlsi.2006.02.00740:2(62-73)Online publication date: Feb-2007
https://doi.org/10.1016/j.vlsi.2006.02.007
Chen RZhou H(2004)Timing macro-modeling of IP blocks with crosstalkProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382563(155-159)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382563
Lin CZhou H(2003)Retiming for Wire Pipelining in System-On-ChipProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009893Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009893

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Robust Optimization of Multiple Timing Constraints

The Jitter Model for Metastability and its Application to Redundant Synchronizers

Fast timing-model independent buffered clock-tree synthesis