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Fakhreddine Ghaffari
Person information
- affiliation: University of Paris-Seine, île-de-France, France
- affiliation: University of Nice Sophia Antipolis, France
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2020 – today
- 2024
- [j13]Arnau Dillen
, Mohsen Omidi
User Evaluation of a Shared Robot Control System Combining BCI and Eye Tracking in a Portable Augmented Reality User Interface. Sensors 24(16): 5253 (2024) - 2023
- [j12]Emmanuel Boutillon
The Syndrome Bit Flipping Algorithm for LDPC Codes. IEEE Commun. Lett. 27(7): 1684-1688 (2023) - [c41]Vivek Bansal, Otmane Aït Mohamed, Fakhreddine Ghaffari:
Layout-based reliability analysis of openMSP430 register file under external radiations. ICM 2023: 294-297 - [c40]Arnau Dillen
Optimal Sensor Set for Decoding Motor Imagery from EEG. NER 2023: 1-4 - 2021
- [j11]Hangxuan Cui
Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 879-891 (2021) - [c39]Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid
FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. DFT 2021: 1-6 - [c38]Fakhreddine Ghaffari, Khoa Le:
An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders. ICECS 2021: 1-6 - [c37]F. Cochachin, Laura Luzzi, Fakhreddine Ghaffari:
Reduced Complexity of a Successive Cancellation Based Decoder for NB-Polar Codes. ISTC 2021: 1-5
2010 – 2019
- 2019
- [j10]Khoa Le
A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 403-416 (2019) - [c36]Hangxuan Cui, Khoa LeTrung, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang:
An Enhanced Offset Min-Sum decoder for 5G LDPC Codes. APCC 2019: 490-495 - [c35]Duc-Phuc Nguyen, Khoa LeTrung, Fakhreddine Ghaffari, David Declercq:
Reliability Enhancement for Multi-level Cell NAND Flash Memory Using Error Asymmetry. APCC 2019: 502-506 - [c34]Khoa LeTrung, Fakhreddine Ghaffari, David Declercq:
An Adaptation of Min-Sum Decoder for 5G Low-Density Parity-Check Codes. ISCAS 2019: 1-5 - [c33]Hangxuan Cui, Khoa Le, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang:
A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes. ISCIT 2019: 616-620 - [c32]Duc-Phuc Nguyen
Performance Enhancement of Polar Codes in Multi-level Cell NAND Flash Memories using Systematic Encoding. ISCIT 2019: 621-626 - [c31]Fakhreddine Ghaffari, Khoa Le, David Declercq:
The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes. NEWCAS 2019: 1-4 - 2018
- [j9]David Declercq
An Imprecise Stopping Criterion Based on In-Between Layers Partial Syndromes. IEEE Commun. Lett. 22(1): 13-16 (2018) - [j8]Khoa Le
Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2183-2195 (2018) - [j7]Burak Unal
Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 3074-3084 (2018) - [j6]Thien Truong Nguyen-Ly
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 508-521 (2018) - [c30]Khoa Le, Fakhreddine Ghaffari:
On the Use of Hard-Decision LDPC Decoders on MLC NAND Flash Memory. SSD 2018: 1453-1458 - [c29]Fakhreddine Ghaffari, Bane Vasic:
Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels. ISCAS 2018: 1-5 - [c28]Khoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin
Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes. ISCAS 2018: 1-5 - [c27]Chris Winstead, Tasnuva Tithi, Emmanuel Boutillon, Fakhreddine Ghaffari:
Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders. ISTC 2018: 1-5 - [c26]Khoa Le, Fakhreddine Ghaffari, David Declercq:
The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes. MWSCAS 2018: 755-758 - [c25]Khoa Le, Fakhreddine Ghaffari, David Declercq:
On the use of Probabilistic Parallel Bit-Flipping decoder for the storage systems. MWSCAS 2018: 948-951 - 2017
- [j5]Khoa Le, Fakhreddine Ghaffari, David Declercq, Bane Vasic:
Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 906-917 (2017) - [j4]Kais Belwafi
A Hardware/Software Prototype of EEG-based BCI System for Home Device Control. J. Signal Process. Syst. 89(2): 263-279 (2017) - [c24]Marc Alexandre Kacou, Fakhreddine Ghaffari, Olivier Romain, Bruno Condamin:
Error rate estimation of a design implemented in an FPGA based on the operating conditions. EWDTS 2017: 1-7 - [c23]Fakhreddine Ghaffari, Ali Akoglu
Multi-Mode Low-Latency Software-Defined Error Correction for Data Centers. ICCCN 2017: 1-8 - [c22]Fakhreddine Ghaffari, Burak Unal
Efficient FPGA implementation of probabilistic gallager B LDPC decoder. ICECS 2017: 178-181 - [c21]Marc Alexandre Kacou, Fakhreddine Ghaffari, Olivier Romain, Bruno Condamin:
FPGA static timing analysis enhancement based on real operating conditions. IECON 2017: 3556-3561 - [c20]Khoa Le, Fakhreddine Ghaffari, David Declercq, Bane Vasic:
Hardware optimization of the perturbation for probabilistic gradient descent bit flipping decoders. ISCAS 2017: 1-4 - [c19]Burak Unal
Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder. NEWCAS 2017: 333-336 - [c18]Yohan Baga, Morgane Richaud, Fakhreddine Ghaffari, Etienne Zante, David Declercq, Michael Nahmiyace:
Probabilistic model of AFDX frames reception for end system backlog assessment. SIES 2017: 1-6 - [i1]Thien Truong Nguyen-Ly, Valentin Savin, Khoa Le, David Declercq, Fakhreddine Ghaffari, Oana Boncalo:
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders. CoRR abs/1709.10396 (2017) - 2016
- [c17]Kais Belwafi
Online Adaptive Filters to Classify Left and Right Hand Motor Imagery. BIOSIGNALS 2016: 335-339 - [c16]Thien Truong Nguyen-Ly
Non-surjective finite alphabet iterative decoders. ICC 2016: 1-6 - [c15]Marc Alexandre Kacou, Fakhreddine Ghaffari, Olivier Romain
Influence of high-power electric motor on an FPGA used in the drive system of electric car. IECON 2016: 4796-4801 - [c14]David Declercq, Chris Winstead, Bane Vasic, Fakhreddine Ghaffari, Predrag Ivanis
Noise-aided gradient descent bit-flipping decoders approaching maximum likelihood decoding. ISTC 2016: 300-304 - 2015
- [c13]Khoa Le, David Declercq, Fakhreddine Ghaffari, Christian Spagnol, Emanuel M. Popovici, Predrag Ivanis
Efficient realization of probabilistic gradient descent bit flipping decoders. ISCAS 2015: 1494-1497 - [c12]Andrei Hera, Oana Boncalo, Constantina-Elena Gavriliu, Alexandru Amaricai, Valentin Savin
Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders. MIXDES 2015: 287-291 - [c11]Truong Nguyen-Ly
FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding. NEWCAS 2015: 1-4 - 2014
- [c10]Kais Belwafi
An embedded implementation of home devices control system based on brain computer interface. ICM 2014: 140-143 - [c9]Fakhreddine Ghaffari, Fouad Sahraoui, Mohamed El Amine Benkhelifa, Bertrand Granado, Marc Alexandre Kacou, Olivier Romain
Fast SRAM-FPGA fault injection platform based on dynamic partial reconfiguration. ICM 2014: 144-147 - [c8]Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado:
Reliability assessment of backward error recovery for SRAM-based FPGAs. IDT 2014: 248-252 - [c7]Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado:
Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overhead. ReConFig 2014: 1-6 - 2013
- [c6]Fouad Sahraoui, Fakhreddine Ghaffari, Mohamed El Amine Benkhelifa, Bertrand Granado:
An efficient BER-based reliability method for SRAM-based FPGA. IDT 2013: 1-6 - 2011
- [j3]Ismail Ktata
Dynamic Application Model for Scheduling with Uncertainty on Reconfigurable Architectures. Int. J. Reconfigurable Comput. 2011: 156946:1-156946:15 (2011) - 2010
- [c5]Ismail Ktata
Prediction performance method for dynamic task scheduling, case study: the OLLAF Architecture. IDT 2010: 97-102 - [c4]Ismail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid:
Novel Approach for Modeling Very Dynamic and Flexible Real Time Applications. ReCoSoC 2010: 21-27
2000 – 2009
- 2009
- [j2]Fakhreddine Ghaffari, Benoît Miramond
Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures. EURASIP J. Embed. Syst. 2009 (2009) - 2008
- [c3]Fakhreddine Ghaffari, Benoît Miramond
Dynamic Adaptation of Hardware-Software Scheduling for Reconfigurable System-on-Chip. IEEE International Workshop on Rapid System Prototyping 2008: 112-118 - 2007
- [j1]Fakhreddine Ghaffari, Michel Auguin, Mohamed Abid, Maher Ben Jemaa:
Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures. Trans. High Perform. Embed. Archit. Compil. 1: 179-193 (2007) - 2006
- [c2]Fakhreddine Ghaffari, Michel Auguin:
An efficient on-line Approach for on-chip HW/SW partitioner and scheduler. ARCS Workshops 2006: 215-223 - 2005
- [c1]Fakhreddine Ghaffari, Michel Auguin, Mohamed Abid, Maher Benjemaa:
An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems. DSD 2005: 379-382
Coauthor Index
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last updated on 2024-10-07 21:17 CEST by the dblp team
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