default search action
27th IOLTS 2021: Torino, Italy
- 27th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2021, Torino, Italy, June 28-30, 2021. IEEE 2021, ISBN 978-1-6654-3370-9
- Kensuke Murakami, Mahfuzul Islam
, Hidetoshi Onodera:
CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models. 1-6 - Chandramouli N. Amarnath, Md Imran Momtaz, Abhijit Chatterjee:
Addressing Soft Error and Security Threats in DNNs Using Learning Driven Algorithmic Checks. 1-4 - Yukiya Miura, Shingo Tsutsumi:
A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay. 1-6 - Andrea Portaluri
A New Domains-based Isolation Design Flow for Reconfigurable SoCs. 1-7 - Franco Oberti, Ernesto Sánchez, Alessandro Savino
TAURUM P2T: Advanced Secure CAN-FD Architecture for Road Vehicle. 1-7 - Oriol Sala, Sergi Alcaide
SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation. 1-7 - Kazuki Yoshisue, Yutaka Masuda, Tohru Ishihara:
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing. 1-7 - Saurabh Khandelwal, Marco Ottavi
A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations. 1-4 - Shuhei Yamamoto, Yuto Sasaki, Yujie Zhao, Jianglin Wei, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Takayuki Nakatani, Minh Tri Tran, Shogo Katayama, Kazumi Hatayama, Haruo Kobayashi:
Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method. 1-6 - Marc Perelló Bacardit, Leonardo Bautista-Gomez, Osman S. Unsal:
FPGA Checkpointing for Scientific Computing. 1-7 - Stéphane Burel, Adrian Evans, Lorena Anghel:
MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators. 1-6 - Mitko Veleski, Michael Hübner, Milos Krstic
Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework. 1-7 - Suvadeep Banerjee
Online Fast Detection and Diagnosis of Power Grid Security Attacks Using State Checksums. 1-7 - Felipe Augusto da Silva
Flip Flop Weighting: A technique for estimation of safety metrics in Automotive Designs. 1-7 - Yuya Isaka, Foisal Ahmed
Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation. 1-6 - Bastien Deveautour, Marcello Traiola
Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing. 1-7 - Tatsuki Kurihara, Nozomu Togawa:
Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random Forests. 1-4 - Yifeng Gao, Hosein Mohammadi Makrani, Mehrdad Aliasgari, Amin Rezaei, Jessica Lin, Houman Homayoun, Hossein Sayadi:
Adaptive-HMD: Accurate and Cost-Efficient Machine Learning-Driven Malware Detection using Microarchitectural Events. 1-7 - Mahsa Akhsham, Zainalabedin Navabi:
Integrating an Interconnect BIST with Crosstalk Avoidance Hardware. 1-6 - Josie E. Rodriguez Condia
Protecting GPU's Microarchitectural Vulnerabilities via Effective Selective Hardening. 1-7 - Annachiara Ruospo
A Suitability Analysis of Software Based Testing Strategies for the On-line Testing of Artificial Neural Networks Applications in Embedded Devices. 1-6 - Tiziano Fiorucci, Jean-Marc Daveau, Giorgio Di Natale, Philippe Roche:
Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems. 1-6 - Kazunari Takasaki, Ryoichi Kida, Nozomu Togawa:
An Anomalous Behavior Detection Method Based on Power Analysis Utilizing Steady State Power Waveform Predicted by LSTM. 1-7 - Sangeet Saha, Adewale Adetomi, Xiaojun Zhai, Server Kasap
EnSuRe: Energy & Accuracy Aware Fault-tolerant Scheduling on Real-time Heterogeneous Systems. 1-4 - Davide Appello
System-Level Test: State of the Art and Challenges. 1-7 - Chih-Hao Wang, Natalia Lylina, Ahmed Atteya, Tong-Yu Hsieh, Hans-Joachim Wunderlich:
Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems. 1-7 - Riccardo Cantoro, Patrick Girard, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement. 1-4 - Sree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Narendra Kumar Pulipati, Joy Chen, Teja Masina:
Robust Adaptive Read Scheme for 7nm Configuration SRAMs. 1-4 - Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa:
Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists. 1-4 - Levent Aksoy
High-level Intellectual Property Obfuscation via Decoy Constants. 1-7 - Francisco Bas, Sergi Alcaide
SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping. 1-7 - Mohamed Elshamy, Haralampos-G. Stratigopoulos:
Neuron-PUF: Physical Unclonable Function Based on a Single Spiking Neuron. 1-6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-22 19:32 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: