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Estimating path delay distribution considering coupling noise

Published: 11 March 2007 Publication History

Abstract

Accurately estimating critical path delays is extremely important for yield optimization and for path selection in delay testing. It is well known that dynamic effects such ascoupling noise can significantly affect critical path delays. In traditional static timing analysis, the coupling effect isincorporated by estimating the switching window overlaps between aggressor and victim and then assuming a constant (worst case) coupling factor if any overlap is present. However in path based statistical timing analysis, using a constant coupling factor can overestimate the mean delay while under estimating the delay variance. In this paper, we propose a technique to estimate the dynamic variation in pathdelay caused by coupling noise. We treat the effective coupling capacitance as a random variable that varies as a function of the relative signal arrival times between victim andaggressor nodes. A modeling technique to estimate the capacitance variation is shown and a framework that gives therelative signal arrival time distribution at the victim nodesis developed.

References

[1]
R. Arunachalam, K. Rajagopal, L. T. Pileggi, TACO: Timing Analysis With Coupling, Proc. of Design Automation Conf., pp 266--269, Los Angeles, CA, June 2000.
[2]
A. Khang, S. Muddu, E. Sarto, On Switch Factor Based Analysis of Coupled RC Interconnects, Design Automation Conf., pp 79--84, 2000.
[3]
S. Sapatnekar, A Timing Model Incorporating the Effect of Crosstalk on Delay and its Application to Optimal Channel Routing, IEEE Tran. on Computer Aided Design, Vol. 19, pp.550--559, 2000.
[4]
D. Sinha and H. Zhou, A Unified Framework for Statistical Timing Analysis with Coupling and Multiple Input Switching, Internation Conf. on Computer Aided Design, pp. 837--843, San Jose, CA, 2005.
[5]
J. Le, X. Li and L. Pileggi, STAC: Statistical Timing with correlation, Proc. of the Design Automation Conf., pp.343--348, 2004.
[6]
K. Agarwal, T.Sato, Y.Cao, D.Slyvester, and C.Hu, Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis, Proc. of 4th Int. Symposium of Quality Electronic Design (ISQED), 2003.
[7]
M. Kulkarni, T. Chen, A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects, Proc. of 5th Int. Symposium of Quality Electronic Design (ISQED), 2004.
[8]
T.M. Mak, A. Kristic, K-T. Cheng, L-C. Wang, New Challenges in Delay Testing of Nanometer Multigigahertz Designs, IEEE CASS, 2004.
[9]
A. Gattiker, S. Nassif, R. Dinakar, C. Long, Timing Yield Estimation from Static Timing Analysis, ISQED 2001.
[10]
J. Grodstein, D. Bhavasar, V. Bettada, R. Davies, Automatic Generation for Critical-Path Tests for a Partial-Scan Microprocessor,ICCD, 2003.
[11]
J.-J. Liou, K.-T. Cheng, S. Kundu and A. Krstic, Fast Statistical Timing Analysis by Probabilistic Event Propagation Proc. of Design Automation Conference, pp. 661--666, June 2001.
[12]
J. H. Friedman. Multivariate adaptive regression splines, Annals of Statistics, Vol. 19, pp. 1--14, 1991.
[13]
C.V. Kashyap, C.J. Alpert, A. Devgan, An Effective Capacitance Based Delay Metric for RC Interconnect Proc. of Int. Conf. on Computer Aided Design, pp. 229--234, San Jose, CA, Nov 2000.
[14]
C. Alpert, A. Devgan, and C. Kashyap, A two moment RC delay metric for performance optimization, ISPD, pp. 69--74, 2000.
[15]
L.C. Wang, J. Liou, K-T. Cheng, Critical Path Selection for Delay Fault Testing Based on Statistical Timing Model, IEEE Tran. on Computer Aided Design for Integrated Circuits and Systems, Vol. 23, pp. 1550--1565, 2004.
[16]
P. Variyam, A.Chatterjee, Specification-Driven Test Design for Analog Circuits, IEEE Intl. Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 335--340, Nov. 1998.
[17]
C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker, S. Narayan, First-Order Incremental Block-Based Statistical Timing Analysis, Design Automation Conference, June 2004.
[18]
B. Stine, et al. A Closed-Form Analytic Modek for ILD Thickness Variation in CMP Processes, Proc. CMP-MIC, Santa Clara, CA, Feb, 1997.

Cited By

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  • (2009)Critical Path Selection for Delay Testing Considering Coupling NoiseJournal of Electronic Testing: Theory and Applications10.1007/s10836-009-5105-725:4-5(213-223)Online publication date: 1-Aug-2009
  • (2008)Modeling crosstalk in statistical static timing analysisProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391715(974-979)Online publication date: 8-Jun-2008

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    cover image ACM Conferences
    GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
    March 2007
    626 pages
    ISBN:9781595936059
    DOI:10.1145/1228784
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 11 March 2007

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    Author Tags

    1. coupling
    2. crosstalk
    3. dynamic delay variation

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    GLSVLSI07: Great Lakes Symposium on VLSI 2007
    March 11 - 13, 2007
    Stresa-Lago Maggiore, Italy

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    • (2009)Critical Path Selection for Delay Testing Considering Coupling NoiseJournal of Electronic Testing: Theory and Applications10.1007/s10836-009-5105-725:4-5(213-223)Online publication date: 1-Aug-2009
    • (2008)Modeling crosstalk in statistical static timing analysisProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391715(974-979)Online publication date: 8-Jun-2008

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