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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 23
Volume 23, Number 1, January 2004
- Robert P. Dick, Niraj K. Jha:
COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems. 2-16 - Ingo Sander
, Axel Jantsch:
System modeling and transformational design refinement in ForSyDe [formal system design]. 17-32 - Ganesh Lakshminarayana, Anand Raghunathan
Common-case computation: a high-level energy and performance optimization technique. 33-49 - Jennifer L. Wong
Optimizing designs using the addition of deflection operations. 50-59 - Robert K. Thalhammer, Gerhard K. M. Wachutka:
Physically rigorous modeling of internal laser-probing techniques for microstructured semiconductor devices. 60-70 - Chris C. N. Chu, Evangeline F. Y. Young:
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. 71-79 - Göran Jerke, Jens Lienig:
Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits. 80-90 - Leendert M. Huisman:
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). 91-101 - Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
Fast postplacement optimization using functional symmetries. 102-118 - Jennifer L. Wong, Gang Qu, Miodrag Potkonjak:
Optimization-intensive watermarking techniques for decision problems. 119-127 - Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
A library compatible driver output model for on-chip RLC transmission lines. 128-136 - Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. 136-141 - Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. 141-147 - Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
Nontree routing for reliability and yield improvement [IC layout]. 148-156 - Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim:
Coupling-aware high-level interconnect synthesis [IC layout]. 157-164 - Irith Pomeranz:
Constrained test generation for embedded synchronous sequential circuits with serial-input access. 164-172
Volume 23, Number 2, February 2004
- Florin Balasa, Sarat C. Maruvada, Karthik Krishnamoorthy:
On the exploration of the solution space in analog placement with symmetry constraints. 177-191 - Giorgio Biagetti, Simone Orcioni
SiSMA-a tool for efficient analysis of analog CMOS integrated circuits affected by device mismatch. 192-207 - Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong:
Effective iterative techniques for fingerprinting design IP. 208-215 - Fei Sun, Srivaths Ravi, Anand Raghunathan
Custom-instruction synthesis for extensible-processor platforms. 216-228 - Geun Rae Cho, Tom Chen:
Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. 229-242 - Mahmut T. Kandemir, J. Ramanujam
A compiler-based approach for dynamically managing scratch-pad memories in embedded systems. 243-260 - Mehdi Baradaran Tahoori, Subhasish Mitra
Techniques and algorithms for fault grading of FPGA interconnect test configurations. 261-272 - B. K. S. V. L. Varaprasad
A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits. 273-287 - Michael W. Beattie, Lawrence T. Pileggi:
Parasitics extraction with multipole refinement. 288-292 - Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira
A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data. 293-301 - Sumit Gupta, Nicolae Savoiu, Nikil D. Dutt
Using global code motions to improve the quality of results for high-level synthesis. 302-312 - Sandip Kundu:
Pitfalls of hierarchical fault simulation. 312-314 - Wai-Kei Mak:
I/O placement for FPGAs with multiple I/O standards. 315-321 - Kohei Miyase, Seiji Kajihara:
XID: Don't care identification of test patterns for combinational circuits. 321-326
Volume 23, Number 3, March 2004
- Rafael Escovar, Roberto Suaya:
Optimal design of clock trees for multigigahertz applications. 329-345 - Jason Cong, Sung Kyu Lim
Edge separability-based circuit clustering with application to multilevel circuit partitioning. 346-357 - Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu:
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. 358-365 - Jinjun Xiong
Full-chip routing optimization with RLC crosstalk budgeting. 366-377 - Sheng Uei Guan, Shu Zhang, Marie Therese Quieta:
2-D CA variation with asymmetric neighborship for pseudorandom number generation. 378-388 - Georges G. E. Gielen
An analytical integration method for the simulation of continuous-time ΔΣ modulators. 389-399 - Olaf Schenk
The effects of unsymmetric matrix permutations and scalings in semiconductor device and circuit simulation. 400-411 - Jun Yuan, Adnan Aziz, Carl Pixley, Ken Albin:
Simplifying Boolean constraint solving for random simulation-vector generation. 412-420 - Subhasish Mitra
X-compact: an efficient response compaction technique. 421-432 - Sujit T. Zachariah, Sreejit Chakravarty:
Extraction of two-node bridges from large industrial circuits. 433-439 - Rolf Drechsler
Synthesis of fully testable circuits from BDDs. 440-443 - Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert:
A delay metric for RC circuits based on the Weibull distribution. 443-447
Volume 23, Number 4, April 2004
- Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick:
Repeater scaling and its impact on CAD. 451-463 - Andrew B. Kahng, Xu Xu:
Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning. 464-471 - Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden:
Benchmarking for large-scale placement and beyond. 472-487 - Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda:
Crosstalk noise control in an SoC physical design flow. 488-497 - Masanori Hashimoto
Equivalent waveform propagation for static timing analysis. 498-508 - Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan:
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. 509-516 - Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze:
Porosity-aware buffered Steiner tree construction. 517-526 - Bo Hu, Malgorzata Marek-Sadowska:
Fine granularity clustering-based placement. 527-536 - Chin-Chih Chang, Jason Cong, Michail Romesis, Min Xie:
Optimality and scalability study of existing placement algorithms. 537-549 - Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
Architecture and synthesis for on-chip multicycle communication. 550-564 - Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen:
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. 565-572 - Yan Feng, Dinesh P. Mehta
Constrained floorplanning using network flows. 572-580 - Robert K. Thalhammer, Gerhard K. M. Wachutka:
Corrections to "Physically Rigorous Modeling of Internal Laser-Probing Techniques for Microstructured Semiconductor Devices". 581-582
Volume 23, Number 5, May 2004
- Dominik Stoffel, Wolfgang Kunz:
Equivalence checking of arithmetic circuits on the arithmetic bit level. 586-597 - Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz:
Structural FSM traversal. 598-619 - Kanishka Lahiri, Anand Raghunathan
Design of high-performance system-on-chips using communication architecture tuners. 620-636 - Subhasis Bhattacharjee
LPRAM: a novel low-power high-performance RAM design with testability and scalability. 637-651 - Yunsi Fei
A hybrid energy-estimation technique for extensible processors. 652-664 - Ashish Srivastava, Dennis Sylvester:
Minimizing total power by simultaneous Vdd/Vth assignment. 665-677 - Luca Daniel, Chin Siong Ong, Sok Chay Low, Kwok Hong Lee, Jacob K. White:
A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models. 678-693 - Iris Hui-Ru Jiang, Yao-Wen Chang
Simultaneous floor plan and buffer-block optimization. 694-703 - Hai Zhou:
Efficient Steiner tree construction based on spanning graphs. 704-710 - Dipak Sitaram, Yu Zheng, Kenneth L. Shepard:
Full-chip, three-dimensional shapes-based RLC extraction. 711-727 - Martin Fischer, Heinz K. Dirks:
Multigranular parallel algorithms for solving linear equations in VLSI circuit simulation. 728-736 - Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers:
Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. 737-757 - Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng:
Efficient test solutions for core-based designs. 758-775 - Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee:
Embedded deterministic test. 776-792 - Yao-Wen Chang
MR: a new framework for multilevel full-chip routing. 793-800 - Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani:
Testing SoC interconnects for signal integrity using extended JTAG architecture. 800-811
Volume 23, Number 6, June 2004
- Thomas Binder, Clemens Heitzinger, Siegfried Selberherr
A study on global and local optimization techniques for TCAD analysis tasks. 814-822 - Adil Koukab, Kaustav Banerjee, Michel J. Declercq:
Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs. 823-836 - Shinji Odanaka:
Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures. 837-842 - Tianhao Zhang, Krishnendu Chakrabarty
Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC. 843-858 - Jennifer L. Wong
Probabilistic constructive optimization techniques. 859-868 - Paul D. Kundarewich, Jonathan Rose:
Synthetic circuit generation using clustering and iteration. 869-887 - Olivier Peyran, Zheng Zeng, Wenjun Zhuang:
Area optimization of delay-optimized structures using intrinsic constraint graphs. 888-906 - Sheldon X.-D. Tan, Chuanjin Richard Shi:
Efficient approximation of symbolic expressions for analog behavioral modeling and analysis. 907-918 - Kanishka Lahiri, Anand Raghunathan
Efficient power profiling for battery-driven embedded system design. 919-932 - Aiman H. El-Maleh
An efficient test relaxation technique for synchronous sequential circuits. 933-940 - Andrew Labun:
Rapid method to account for process variation in full-chip capacitance extraction. 941-951 - Kanishka Lahiri, Anand Raghunathan
Design space exploration for optimizing on-chip communication architectures. 952-961 - Laurent Latorre, Vincent Beroulle, Pascal Nouet:
Design of CMOS MEMS based on mechanical resonators using a RF simulation approach. 962-967 - Jai-Ming Lin, Yao-Wen Chang
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. 968-980 - Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas:
A unified framework for generating all propagation functions for logic errors and events. 980-986 - Jennifer L. Wong
Computational forensic techniques for intellectual property protection. 987-994
Volume 23, Number 7, July 2004
- Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida:
Skew measurements in clock distribution circuits using an analytic signal method. 997-1009 - Weidong Wang, Anand Raghunathan
Resource budgeting for Multiprocess High-level synthesis. 1010-1019 - Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
SPFD-based wire removal in standard-cell and network-of-PLA circuits. 1020-1030 - Peter Petrov, Alex Orailoglu:
Tag compression for low power in dynamically customizable embedded processors. 1031-1047 - Xun Liu, Marios C. Papaefthymiou:
A Markov chain sequence generator for power macromodeling. 1048-1062 - Eng Teo Ong, Heow Pueh Lee, Kian Meng Lim
A parallel fast Fourier transform on multipoles (FFTM) algorithm for electrostatics analysis of three-dimensional structures. 1063-1072 - Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang
Multilevel circuit clustering for delay minimization. 1073-1085 - Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai:
Area minimization of power distribution network using efficient nonlinear programming techniques. 1086-1094 - Sheng Uei Guan, Syn Kiat Tan:
Pseudorandom number generation with self-programmable cellular automata. 1095-1101 - Ying-Tsai Chang, Kwang-Ting Cheng
Self-referential verification for gate-level implementations of arithmetic circuits. 1102-1112 - Edmund M. Clarke, Anubhav Gupta, Ofer Strichman
SAT-based counterexample-guided abstraction refinement. 1113-1123 - Ching-An Lin, Chien-Hsien Wu:
Second-order approximations for RLC trees. 1124-1128 - Mohsen Nahvi, André Ivanov:
Indirect test architecture for SoC testing. 1128-1142 - Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. 1142-1153
Volume 23, Number 8, August 2004
- Weiping Shi, Fangqing Yu:
A divide-and-conquer algorithm for 3-D capacitance extraction. 1157-1163 - Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram:
Transition reduction in memory buses using sector-based encoding techniques. 1164-1174 - Jiong Luo, Lin Zhong, Yunsi Fei
Register binding-based RTL power management for control-flow intensive designs. 1175-1183 - Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi
Optimal integer delay-budget assignment on directed acyclic graphs. 1184-1199 - Qing Huo Liu
The spectral grid method: a novel fast Schrodinger-equation solver for semiconductor nanodevice simulation. 1200-1208 - Loc Vu-Quoc
Efficient simulation of coupled circuit-field problems: generalized Falk method. 1209-1219 - Ketan N. Patel, John P. Hayes, Igor L. Markov:
Fault testing for reversible circuits. 1220-1230 - Aseem Agarwal, Vladimir Zolotov, David T. Blaauw:
Statistical clock skew analysis considering intradie-process variations. 1231-1242 - Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Logic of constraints: a quantitative performance and functional constraint formalism. 1243-1255 - Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas:
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. 1256-1263 - Yehea I. Ismail, Chirayu S. Amin:
Computation of signal-threshold crossing times directly from higher order moments. 1264-1276
Volume 23, Number 9, September 2004
- James C. Hoe, Arvind:
Operation-centric hardware description and synthesis. 1277-1288 - Lei Li, Krishnendu Chakrabarty
Test set embedding for deterministic BIST using a reconfigurable interconnection network. 1289-1305 - Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Ring generators - new devices for embedded test applications. 1306-1320 - Yungseon Eo, Seongkyun Shin, William R. Eisenstadt
A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching. 1321-1337 - Hai Zhou, Chuan Lin:
Retiming for wire pipelining in system-on-chip. 1338-1345 - Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
A simple metric for slew rate of RC circuits based on two circuit moments. 1346-1354 - Xiaoliang Bai, Sujit Dey:
High-level crosstalk defect Simulation methodology for system-on-chip interconnects. 1355-1361 - Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt
IDAP: a tool for high-level power estimation of custom array structures. 1361-1369 - Bren Mochocki, Xiaobo Sharon Hu
A unified approach to variable voltage scheduling for nonideal DVS processors. 1370-1377 - Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato
Probabilistic crosstalk delay estimation for ASICs. 1377-1383
Volume 23, Number 10, October 2004
- Vishnu Swaminathan, Krishnendu Chakrabarty
Network flow techniques for dynamic voltage scaling in hard real-time systems. 1385-1398 - Nele V. T. D'Halleweyn, James Benson, William Redman-White, Ketan Mistry, M. Swanenberg:
MOOSE: a physically based compact DC model of SOI LD MOSFETs for analogue circuit simulation. 1399-1410 - Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy:
A circuit-compatible model of ballistic carbon nanotube field-effect transistors. 1411-1420 - Rouying Zhan, Haigang Feng, Qiong Wu, Haolu Xie, Xiaokang Guan, Guang Chen, Albert Z. Wang:
ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism. 1421-1428 - Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos:
Multiphase BIST: a new reseeding technique for high test-data compression. 1429-1446 - Chunsheng Liu, Krishnendu Chakrabarty
Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip. 1447-1459 - Alexander Korshak:
Noise-rejection model based on charge-transfer equation for digital CMOS circuits. 1460-1468 - Irith Pomeranz:
Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains. 1465-1478 - Kaijie Wu, Ramesh Karri
Fault secure datapath synthesis using hybrid time and hardware redundancy. 1476-1485 - Jing-Ling Yang, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
A high-efficiency strongly self-checking asynchronous datapath. 1484-1494 - Julio Guillermo Zola:
Simple model of metal oxide varistor for Pspice Simulation. 1491-1494
Volume 23, Number 11, November 2004
- Dmitri Maslov, Gerhard W. Dueck:
Reversible cascades with minimal garbage. 1497-1509 - Bogdan Tutuianu, Ross Baldick, Mark S. Johnstone:
Nonlinear driver models for timing and noise analysis. 1510-1521 - Hua Xiang, Xiaoping Tang, Martin D. F. Wong
Bus-driven floorplanning. 1522-1530 - Kyeong Keol Ryu, Vincent John Mooney III:
Automated bus generation for multiprocessor SoC design. 1531-1549 - Li-C. Wang
Critical path selection for delay fault testing based upon a statistical timing model. 1550-1565 - Jennifer L. Wong
Fair watermarking using combinatorial isolation lemmas. 1566-1574 - Dipanjan Gope, Vikram Jandhyala:
Oct-tree-based multilevel low-rank decomposition algorithm for rapid 3-D parasitic extraction. 1575-1580 - Safar Hatami, M. Yaser Azizi, Hamid-Reza Bahrami, Davoud Motavalizadeh-Naeini, Ali Afzali-Kusha:
Accurate and efficient modeling of SOI MOSFET with technology independent neural networks. 1580-1587 - Irith Pomeranz, Sudhakar M. Reddy:
Vector-restoration-based static compaction using random initial omission. 1587-1592 - David J. Walkey, Tom J. Smy, Dritan Celo, Tom W. MacElwee, Michael C. Maliepaard:
Compact, netlist-based representation of thermal transient coupling using controlled sources. 1593-1596
Volume 23, Number 12, December 2004
- Ulrich Brenner, Jens Vygen:
Legalizing a placement with minimum total movement. 1597-1613 - Haihua Su, Jiang Hu, Sachin S. Sapatnekar
A methodology for the simultaneous design of supply and signal networks. 1614-1624 - Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr:
A universal technique for fast and flexible instruction-set architecture simulation. 1625-1639 - Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On the characterization and efficient computation of hard-to-detect bridging faults. 1640-1649 - Biplab K. Sikdar
Generation of test patterns without prohibited pattern set. 1650-1660 - Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan:
Closed-form delay and slew metrics made easy. 1661-1669 - Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Postroute gate sizing for crosstalk noise reduction. 1670-1677 - Tom Chen, Amjad Hajjar:
Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics. 1677-1683 - Jason Cong, Sung Kyu Lim
Retiming-based timing analysis with an application to mincut-based global placement. 1684-1692 - Manoj Kumar Jain
An efficient technique for exploring register file size in ASIP design. 1693-1699
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