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Prashant Saxena
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2020 – today
- 2024
- [i5]Masoud Ahmadi, Andrew McBride, Paul Steinmann, Prashant Saxena:
Plane stress finite element modelling of arbitrary compressible hyperelastic materials. CoRR abs/2410.22562 (2024) - 2022
- [j12]T. Patrick Xiao
, Ben Feinberg
An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1480-1493 (2022) - [i4]Zhaowei Liu, Andrew McBride, Abhishek Ghosh, Luca Heltai, Weicheng Huang, Tiantang Yu, Paul Steinmann, Prashant Saxena:
Computational bifurcation analysis of hyperelastic thin shells. CoRR abs/2210.15854 (2022) - 2021
- [c23]Bhumika Shah, Ankita Sinha, Prashant Saxena:
Image GPT with Super Resolution. FICTA (1) 2021: 99-107 - [i3]Zhaowei Liu, Andrew McBride, Prashant Saxena, Luca Heltai, Yilin Qu, Paul Steinmann:
Vibration Analysis of Piezoelectric Kirchhoff-Love Shells based on Catmull-Clark Subdivision Surfaces. CoRR abs/2105.09288 (2021) - [i2]T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Venkatraman Prabhakar, Prashant Saxena, Vineet Agrawal, Sapan Agarwal, Matthew J. Marinella:
On the Accuracy of Analog Neural Network Inference Accelerators. CoRR abs/2109.01262 (2021)
2010 – 2019
- 2019
- [i1]Zhaowei Liu, Andrew McBride, Prashant Saxena, Paul Steinmann:
Aspects of Isogeometric Analysis with Catmull-Clark Subdivision Surfaces. CoRR abs/1909.11180 (2019) - 2017
- [c22]Wei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena:
Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. ISPD 2017: 15-21 - 2014
- [c21]Haris Volos, Sanketh Nalli, Sankaralingam Panneerselvam, Venkatanathan Varadarajan, Prashant Saxena, Michael M. Swift:
Aerie: flexible file-system interfaces to storage-class memory. EuroSys 2014: 14:1-14:14 - 2012
- [c20]Tong Gao, Prashant Saxena:
On pioneering nanometer-era routing problems. ISPD 2012: 65-68 - 2011
- [j11]Prashant Saxena, Yao-Wen Chang
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 165-166 (2011) - [c19]Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho:
Multi-mode redundancy removal. ISQED 2011: 791-799 - 2010
- [j10]Gi-Joon Nam, Prashant Saxena:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 169-170 (2010) - [e2]Prashant Saxena, Yao-Wen Chang:
Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010. ACM 2010, ISBN 978-1-60558-920-6 [contents]
2000 – 2009
- 2009
- [c18]Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer
On improving optimization effectiveness in interconnect-driven physical synthesis. ISPD 2009: 51-58 - [e1]Gi-Joon Nam, Prashant Saxena:
Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009. ACM 2009, ISBN 978-1-60558-449-2 [contents] - 2008
- [r1]Rupesh S. Shelar, Prashant Saxena:
Estimation of Routing Congestion. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [b2]Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar:
Routing Congestion in VLSI Circuits - Estimation and Optimization. Series on Integrated Circuits and Systems, Springer 2007, ISBN 978-0-387-30037-5, pp. I-XIV, 1-248 - 2006
- [j9]Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 625-636 (2006) - [j8]Prashant Saxena:
On controlling perturbation due to repeaters during quadratic placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1733-1743 (2006) - [c17]Prashant Saxena:
The scaling of interconnect buffer needs. SLIP 2006: 109-112 - 2005
- [j7]Rupesh S. Shelar, Sachin S. Sapatnekar
A predictive distributed congestion metric with application to technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 696-710 (2005) - [c16]Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda:
A perturbation-aware noise convergence methodology for high frequency microprocessors. ASP-DAC 2005: 717-722 - [c15]Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar:
Net weighting to reduce repeater counts during placement. DAC 2005: 503-508 - [c14]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani:
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233 - [c13]Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar:
An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD 2005: 137-144 - 2004
- [j6]Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick:
Repeater scaling and its impact on CAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 451-463 (2004) - [c12]Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang:
Realizable parasitic reduction for distributed interconnects using matrix pencil technique. ASP-DAC 2004: 780-785 - [c11]Prashant Saxena, Bill Halpin:
Modeling repeaters explicitly within analytical placement. DAC 2004: 699-704 - [c10]Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester:
The great interconnect buffering debate: are you a chicken or an ostrich? ISPD 2004: 61 - [c9]Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang:
A predictive distributed congestion metric and its application to technology mapping. ISPD 2004: 210-217 - 2003
- [j5]Prashant Saxena, Satyanarayan Gupta:
On integrating power and signal routing for shield count minimization in congested regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 437-445 (2003) - [j4]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang:
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 879-887 (2003) - [c8]Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick:
The scaling challenge: can correct-by-construction design help? ISPD 2003: 51-58 - 2002
- [c7]B. Chappell, Xinning Wang, Priyadarsan Patra
A System-Level Solution to Domino Synthesis with 2 GHz Application. ICCD 2002: 164- - [c6]Prashant Saxena, Satyanarayan Gupta:
Shield count minimization in congested regions. ISPD 2002: 78-83 - 2001
- [j3]Prashant Saxena, C. L. Liu:
Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 503-515 (2001) - [c5]Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang:
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737 - 2000
- [j2]Prashant Saxena, C. L. Liu:
A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6): 691-702 (2000)
1990 – 1999
- 1999
- [c4]Prashant Saxena, C. L. Liu:
Crosstalk Minimization Using Wire Perturbations. DAC 1999: 100-103 - [c3]Prashant Saxena, Peichen Pan, C. L. Liu:
The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design 1999: 402-407 - 1998
- [b1]Prashant Saxena:
The Retiming and Routing of VLSI Circuits. University of Illinois Urbana-Champaign, USA, 1998 - [c2]Prashant Saxena, C. L. Liu:
A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD 1998: 124-127 - 1996
- [c1]Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu:
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831 - 1994
- [j1]Aviezri S. Fraenkel, Edward M. Reingold, Prashant Saxena:
Efficient Management of Dynamic Tables. Inf. Process. Lett. 50(1): 25-30 (1994)
Coauthor Index
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