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Stephen T. Quay
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2010 – 2019
- 2018
- [c16]Jiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam:
Interconnect Optimization Considering Multiple Critical Paths. ISPD 2018: 132-138
2000 – 2009
- 2008
- [c15]Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia:
Fast interconnect synthesis with layer assignment. ISPD 2008: 71-77 - 2007
- [j8]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
Techniques for Fast Physical Synthesis. Proc. IEEE 95(3): 573-599 (2007) - [c14]Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud:
Fast Electrical Correction Using Resizing and Buffering. ASP-DAC 2007: 553-558 - [c13]Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar
, Weiping Shi:
Probabilistic Congestion Prediction with Partial Blockages. ISQED 2007: 841-846 - [c12]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
The nuts and bolts of physical synthesis. SLIP 2007: 89-94 - 2004
- [j7]Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 136-141 (2004) - [j6]Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze:
Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 517-526 (2004) - [c11]Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay:
Fast and flexible buffer trees that navigate the physical layout environment. DAC 2004: 24-29 - [c10]Charles J. Alpert, Milos Hrkic, Stephen T. Quay:
A fast algorithm for identifying good buffer insertion candidate locations. ISPD 2004: 47-52 - 2003
- [j5]Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham:
Buffer insertion with adaptive blockage avoidance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 492-498 (2003) - [c9]Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay:
Porosity aware buffered steiner tree construction. ISPD 2003: 158-165 - 2002
- [j4]Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay:
Correction to "interconnect synthesis without wire tapering". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 497-497 (2002) - [c8]Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham:
Buffer insertion with adaptive blockage avoidance. ISPD 2002: 92-97 - [c7]Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109 - 2001
- [j3]Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay:
Interconnect synthesis without wire tapering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 90-104 (2001) - [j2]Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 556-562 (2001) - [c6]Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar:
Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402 - [c5]Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia:
Buffered Steiner trees for difficult instances. ISPD 2001: 4-9 - 2000
- [c4]José Luis Neves, Stephen T. Quay:
Buffer Library Selection. ICCD 2000: 221-226
1990 – 1999
- 1999
- [j1]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Buffer insertion for noise and delay optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1633-1645 (1999) - [c3]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Buffer Insertion with Accurate Gate and Interconnect Delay Computation. DAC 1999: 479-484 - [c2]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Is wire tapering worthwhile? ICCAD 1999: 430-436 - 1998
- [c1]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Buffer Insertion for Noise and Delay Optimization. DAC 1998: 362-367
Coauthor Index
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