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Hannah Honghua Yang
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2010 – 2019
- 2016
- [r2]Martin D. F. Wong, Hannah Honghua Yang:
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach. Encyclopedia of Algorithms 2016: 295-301
2000 – 2009
- 2008
- [r1]Hannah Honghua Yang, Martin D. F. Wong:
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach. Encyclopedia of Algorithms 2008 - 2007
- [j15]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 645-658 (2007) - [j14]Hsun-Cheng Lee, Yao-Wen Chang
, Hannah Honghua Yang:
MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1430-1444 (2007) - 2006
- [j13]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2637-2646 (2006) - [j12]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani:
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006) - [c17]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185 - 2005
- [c16]Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong:
Microarchitecture evaluation with floorplanning and interconnect pipelining. ASP-DAC 2005: 8-15 - [c15]Guowu Yang, Xiaoyu Song, Hannah Honghua Yang, Fei Xie:
A Theoretical Upper Bound for IP-Based Floorplanning. COCOON 2005: 411-419 - 2004
- [j11]Yan Feng, Dinesh P. Mehta
Constrained floorplanning using network flows. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 572-580 (2004) - [c14]Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu:
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ISCAS (5) 2004: 81-84 - 2003
- [j10]Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani:
Integrated floorplanning with buffer/channel insertion for bus-based designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 730-741 (2003) - [c13]Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang:
Multilevel floorplanning/placement for large-scale modules using B*-trees. DAC 2003: 812-817 - [c12]Yan Feng, Dinesh P. Mehta
Constrained "Modern" Floorplanning. ISPD 2003: 128-135 - 2002
- [c11]Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani:
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. ISPD 2002: 56-61 - 2001
- [j9]Evangeline F. Y. Young, Martin D. F. Wong
On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 800-807 (2001) - [c10]Hung-Ming Chen, D. F. Wong
Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI 2001: 62-67 - 2000
- [j8]Evangeline F. Y. Young, Martin D. F. Wong
Slicing floorplans with range constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 272-278 (2000)
1990 – 1999
- 1999
- [j7]Evangeline F. Y. Young, Martin D. F. Wong
Slicing floorplans with boundary constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1385-1389 (1999) - [c9]Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong
Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357 - [c8]Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman:
Logic Verification of Very Large Circuits Using Shark. VLSI Design 1999: 310-317 - 1998
- [j6]Hannah Honghua Yang, Martin D. F. Wong
Optimal min-area min-cut replication in partitioned circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11): 1175-1183 (1998) - 1997
- [j5]Vijaya Ramachandran, Honghua Yang:
An Efficient Parallel Algorithm for the Layered Planar Monotone Circuit Value Problem. Algorithmica 18(3): 384-404 (1997) - [j4]Hannah Honghua Yang, Martin D. F. Wong
Circuit clustering for delay minimization under area and pin constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 976-986 (1997) - 1996
- [j3]Vijaya Ramachandran, Honghua Yang:
An Efficient Parallel Algorithm for the General Planar Monotone Circuit Value Problem. SIAM J. Comput. 25(2): 312-339 (1996) - [j2]Hannah Honghua Yang, Martin D. F. Wong
Balanced partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1533-1540 (1996) - 1995
- [c7]Honghua Yang, D. F. Wong
Circuit clustering for delay minimization under area and pin constraints. ED&TC 1995: 65-70 - [c6]Hannah Honghua Yang, D. F. Wong
New algorithms for min-cut replication in partitioned circuits. ICCAD 1995: 216-222 - 1994
- [j1]Vijaya Ramachandran, Honghua Yang:
Finding the Closed Partition of a Planar Graph. Algorithmica 11(5): 443-468 (1994) - [c5]Honghua Yang, D. F. Wong
Efficient network flow based min-cut balanced partitioning. ICCAD 1994: 50-55 - [c4]Hannah Honghua Yang, D. F. Wong
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. ICCAD 1994: 150-155 - [c3]Vijaya Ramachandran, Honghua Yang:
An Efficient Parallel Algorithm for the General Planar Monotone Circuit Value Problem. SODA 1994: 622-631 - 1993
- [c2]Vijaya Ramachandran, Honghua Yang:
An Efficient Parallel Algorithm for the Layered Planar Monotone Circuit Value Problem. ESA 1993: 321-332 - 1991
- [c1]Honghua Yang:
An NC algorithm for the general planar monotone circuit value problem. SPDP 1991: 196-203
Coauthor Index
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