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3DIC 2009: San Francisco, California, USA
- IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009. IEEE 2009, ISBN 978-1-4244-4511-0
- Patrick Leduc, Myriam Assous, Léa Di Cioccio, Marc Zussy, Thomas Signamarcheix, Antonio Roman, Maxime Rousseau, Sophie Verrun, Laurent Bally, David Bouchu, Lionel Cadix, Alexis Farcy, Nicolas Sillon:
First integration of Cu TSV using die-to-wafer direct bonding and planarization. 1-5 - Kang Wook Lee, Shigeyuki Kanno, Yuki Ohara, Kouji Kiyoyama, Ji Chel Bea, Takafumi Fukushima
, Tetsu Tanaka
Heterogeneous integration technology for MEMS-LSI multi-chip module. 1-6 - Jan Van Olmen, Jan Coenen, Wim Dehaene, Kristin De Meyer, Cedric Huyghebaert, Anne Jourdain, Guruprasad Katti, Abdelkarim Mercha, Michal Rakowski, Michele Stucchi, Youssef Travaly, Eric Beyne
3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). 1-5 - Samuel J. Dickerson, Steven P. Levitan, Donald M. Chiarulli:
3D integrated circuits for lab-on-chip applications. 1-8 - Thorlindur Thorolfsson, Samson Melamed
Comparative analysis of two 3D integration implementations of a SAR processor. 1-4 - Marcel Demarteau
Developments of novel vertically integrated pixel sensors in the high energy physics community. 1-7 - Morihiro Kada:
Development of Functionally innovative 3D-Integrated Circuit (Dream Chip) technology / High-Density 3D-Integration Technology for Multifunctional Devices. 1-6 - Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerasekera
3-D memory organization and performance analysis for multi-processor network-on-chip architecture. 1-7 - Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi:
Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. 1-4 - Ric van Doremalen, Piet van Engen, Wouter Jochems, Shi Cheng, Thomas Fritzsch, Walter De Raedt:
Miniature wireless activity monitor using 3D system integration. 1-7 - Lionel Cadix, Alexis Farcy, Cédric Bermond, Christine Fuchs, Patrick Leduc, Maxime Rousseau, Myriam Assous, Alexandre Valentian, Julie Roullard, Elie Eid, Nicolas Sillon, Bernard Fléchet, Pascal Ancey:
Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits. 1-7 - Thomas Whipple, Taranjit Kukal, Keith Felton, Vassilios Gerousis:
IC-package co-design and analysis for 3D-IC designs. 1-6 - Tomokatsu Mizukusa, Tamio Nagano, Yasuo Shimizu, Kazuyuki Sakata, Kazuo Kato:
Development of feed-forward design system for rapid SiP design. 1-4 - Dragomir Milojevic
Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study. 1-6 - Yaoyao Ye, Lian Duan, Jiang Xu
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). 1-6 - Christopher Mineo, William Rhett Davis
The benefits of 3D networks-on-chip as shown with LDPC decoding. 1-8 - Seyyed Ahmad Razavi, Morteza Saheb Zamani
A tileable switch module architecture for homogeneous 3D FPGAs. 1-4 - Kouji Kiyoyama, Yuki Ohara, Kang Wook Lee, Y. Yang, Takafumi Fukushima
A parallel ADC for high-speed CMOS image processing system with 3D structure. 1-4 - Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
A capacitive coupling interface with high sensitivity for wireless wafer testing. 1-5 - Panagiotis Asimakopoulos, Geert Van der Plas, Alexandre Yakovlev
Evaluation of energy-recovering interconnects for low-power 3D stacked ICs. 1-5 - Dean L. Lewis, Hsien-Hsin S. Lee:
Architectural evaluation of 3D stacked RRAM caches. 1-4 - Nauman H. Khan, Syed M. Alam, Soha Hassoun:
Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. 1-7 - Julie Roullard, Stéphane Capraro, Thierry Lacrevaz, Lionel Cadix, Elie Eid, Alexis Farcy, Bernard Fléchet:
Influence of 3D integration on 2D interconnections and 2D self inductors HF properties. 1-6 - Qi Wu, Kenneth Rose, Jian-Qiang Lu, Tong Zhang:
Impacts of though-DRAM vias in 3D processor-DRAM integrated systems. 1-6 - Thomas Fritzsch, Raul Mrossko, Tobias Baumgartner, Michael Toepper, Matthias Klein, Jürgen Wolf, Bernhard Wunderle
3-D thin chip integration technology - from technology development to application. 1-8 - Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen
Impact of 3D design choices on manufacturing cost. 1-5 - Shari Farrens:
Evolution of bond technology to hybridized process flows. 1-4 - Ramakanth Alapati, Youssef Travaly, Jan Van Olmen, Ricardo Cotrin Teixeira
TSV metrology and inspection challenges. 1-4 - Laura Mirkarimi, M. Huynh, Piyush Savalia, Vage Oganesian:
3D interconnects for dense die stack packages. 1-5 - G. Williams, Patrick O'Hara, J. Moore, Bart Gordon, J. Rose:
A review of wafer bonding materials and characterizations to enable wafer thinning, backside processing, and laser dicing. 1 - Koichi Takemura, Katsuya Kikuchi, Chihiro Ueda, Kazuhiro Baba, Masahiro Aoyagi, Kanji Otsuka:
SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integration. 1-5 - Menglin Tsai, Amy Klooz, Alexander Leonard, Jennie Appel, Paul D. Franzon:
Through Silicon Via(TSV) defect/pinhole self test circuit for 3D-IC. 1-8 - John F. McDonald, Okan Erdogan, Philip Jacob, Paul M. Belemjian, Alexey Gutin, Aamir Zia, Michael Chu, Jin Woo Kim, Ryan Clarke, Nate DeSimone, Sherry Liu, Russell P. Kraft:
Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers. 1-7 - Tomohide Murase, Hiroyuki Aikyou, Fumikazu Mizutani, Yu Shoji, Tomoya Higashihara, Mitsuru Ueda:
Thermotropic liquid crystalline polyimides toward high heat conducting materials for 3D chip stack. 1-4 - Ji Chel Bea, Mariappan Murugesan, Yuki Ohara, Akihiro Noriki
Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. 1-5 - Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin:
Arithmetic unit design using 180nm TSV-based 3D stacking technology. 1-4 - Ryusuke Egawa, Jubee Tada, Hiroaki Kobayashi, Gensuke Goto:
Evaluation of fine grain 3-D integrated arithmetic units. 1-8 - Eun Chu Oh, Paul D. Franzon:
Technology impact analysis for 3D TCAM. 1-5 - Yoshiyuki Kaiho, Yuki Ohara, Hirotaka Takeshita, Kouji Kiyoyama, Kang Wook Lee, Tetsu Tanaka
3D integration technology for 3D stacked retinal chip. 1-4 - David Henry, Séverine Cheramy, Jean Charbonnier, Pascal Chausse, Muriel Neyret, Cathy Brunet-Manquat, Sophie Verrun, Nicolas Sillon, Laurent Bonnot, Xavier Gagnard, E. Saugier:
3D integration technology for set-top box application. 1-7 - Weng Hong Teh, Raymond Caramto, Jamal Qureshi, Sitaram Arkalgud, M. O'Brien, T. Gilday, Kou Maekawa, T. Saito, Kouichi Maruyama, Thenappan Chidambaram, Wei Wang, David Marx, David Grant, Russ Dudley:
A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration. 1-5 - Yann Civale, Deniz Sabuncuoglu Tezcan, Harold G. G. Philipsen
Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. 1-4 - Adam Beece, Kenneth Rose, Tong Zhang, Jiang-Qian Lu:
Impact of parameter accuracy on 3D design. 1-7 - Kelli Ireland, Donald M. Chiarulli, Steven P. Levitan:
A routerless system level interconnection network for 3D integrated systems. 1-6 - Xi Chen, William Rhett Davis
Delay analysis and design exploration for 3D SRAM. 1-4 - Akihiro Horibe, Fumiaki Yamada:
Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill. 1-4 - Chang-Lee Chen, D.-R. Yost, Jeffrey M. Knecht, David C. Chapman, Douglas C. Oakley, Leonard J. Mahoney, Joseph P. Donnelly, Antonio M. Soares, Vyshnavi Suntharalingam, Robert Berger, V. Bolkhovsky, W. Hu, Bruce D. Wheeler, Craig L. Keast, David C. Shaver:
Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits. 1-4 - Claudio Truzzi, Frédéric Raynal, Vincent Mevellec:
Wet-process deposition of TSV liner and metal films. 1-6 - Seung Wook Yoon, Jae Hoon Ku, Nathapong Suthiwongsunthorn, Pandi Chelvam Marimuthu, Flynn Carson:
Fabrication and packaging of microbump interconnections for 3D TSV. 1-5 - Bioh Kim, Thorsten Matthias, Markus Wimplinger, Paul Lindner:
Advanced wafer bonding solutions for TSV integration with thin wafers. 1-6 - Keith Buchanan, Stephen Burgess, Kathrine Giles, Matthew Muggeridge, Hao Zhao:
Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processing. 1-4 - Roberto Cardu, Mauro Scandiuzzo, Salvatore Cani, Luca Perugini, Eleonora Franchi, Roberto Canegallo, Roberto Guerrieri:
Chip-to-chip communication based on capacitive coupling. 1-6 - James Hermanowski:
Thin wafer handling - Study of temporary wafer bonding materials and processes. 1-5 - Elie Eid, Thierry Lacrevaz, Sébastien de Rivaz, Cédric Bermond, Bernard Fléchet, Françis Calmon, Christian Gontrand, Alexis Farcy, Lionel Cadix, Pascal Ancey:
Predictive High Frequency effects of substrate coupling in 3D integrated circuits stacking. 1-6 - Chuichi Miyazaki, Haruo Shimamoto, Toshihide Uematsu, Yoshiyuki Abe:
Development of wafer thinning and dicing technology for thin wafer. 1-4 - Dau Fatt Lim, Shiv Govind Singh, Xiao Fang Ang, Jun Wei, Chee Mang Ng, Chuan Seng Tan
Achieving low temperature Cu to Cu diffusion bonding with self assembly monolayer (SAM) passivation. 1-5 - Keiji Matsumoto, Soichiro Ibaraki, Katsuyuki Sakuma
Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stack. 1-5 - Zheng Xu, Adam Beece, Kenneth Rose, Tong Zhang, Jian-Qiang Lu:
Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration. 1-9 - Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott C. Smith:
Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. 1-5 - Roshan Weerasekera
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 1-8 - Tapobrata Bandyopadhyay, Ritwik Chatterjee, Daehyun Chung, Madhavan Swaminathan, Rao R. Tummala:
Electrical modeling of Through Silicon and Package Vias. 1-8 - Nauman H. Khan, Syed M. Alam, Soha Hassoun:
System-level comparison of power delivery design for 2D and 3D ICs. 1-7 - Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 1-7 - Yusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa
3D on-chip memory for the vector architecture. 1-6 - Grzegorz Janczyk, Tomasz Bieniek, Jerzy Szynka, Piotr Grabiec:
Reliability aspects of 3D-oriented heterogeneous device design related to stress sensitivity of MOS transistors. 1-6 - Seung Wook Yoon, Dae Wook Yang, Jae Hoon Koo, Meenakshi Padmanathan, Flynn Carson:
3D TSV processes and its assembly/packaging technology. 1-5 - David Marx, David Grant, Russ Dudley, Andy Rudack, W. H. Teh:
Wafer Thickness Sensor (WTS) for etch depth measurement of TSV. 1-5 - Paul Enquist, G. Fountain, C. Petteway, A. Hollingsworth, H. Grady:
Low Cost of Ownership scalable copper Direct Bond Interconnect 3D IC technology for three dimensional integrated circuit applications. 1-6 - Léa Di Cioccio, Pierric Gueguen, Rachid Taibi, Thomas Signamarcheix, Laurent Bally, Laurent Vandroux, Marc Zussy, Sophie Verrun, Jérôme Dechamp, Patrick Leduc, Myriam Assous, David Bouchu, François de Crecy, Laurent-Luc Chapelon, Laurent Clavelier:
An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling. 1-4 - Filip Crnogorac, Ryan P. Birringer, Reinhold H. Dauskardt, R. Fabian R. Pease:
Aluminum-Germanium eutectic bonding for 3D integration. 1-5 - Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma
10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. 1-6 - Samson Melamed
Junction-level thermal extraction and simulation of 3DICs. 1-7 - Thomas Brunschwiler, Stephan Paredes, Ute Drechsler, Bruno Michel, W. Cesar, G. Töral, Yuksel Temiz, Yusuf Leblebici:
Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks. 1-10 - Shiv Govind Singh, Chuan Seng Tan
Impact of thermal through silicon via (TTSV) on the temperature profile of multi-layer 3-D device stack. 1-4 - Moishe Groger, Shadi M. Harb, Devin Morris, William R. Eisenstadt
High speed I/O and thermal effect characterization of 3D stacked ICs. 1-5 - Jianyong Xie, Daehyun Chung, Madhavan Swaminathan, Michael McAllister, Alina Deutsch, Lijun Jiang, Barry J. Rubin:
Electrical-thermal co-analysis for power delivery networks in 3D system integration. 1-4 - Katsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio Gomyo, Yukiharu Takeuchi, Toshikazu Okubo, Kazuhiro Baba, Masahiro Aoyagi, Toshio Sudo, Kanji Otsuka:
Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates. 1-4 - Amadine Jouve, Wenbin Hong, D. Blumenshine, JoElle Dachsteiner, Rama Puligadda, Dongshun Bai, J. Diaz, David Henry:
Material improvement for ultrathin-wafer handling in TSV creation and PECVD process. 1-5 - Takafumi Fukushima
Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch. 1-4 - Lisa G. McIlrath, Wahid Ahmed, Andrew Yip:
Design tools for the 3D roadmap. 1-4 - Matthew Hogan, Dusan Petranovic:
Robust verification of 3D-ICs: Pros, cons and recommendations. 1-6
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