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Michele Stucchi
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2020 – today
- 2024
- [c25]P. Zhao, Liesbeth Witters, Anne Jourdain, Michele Stucchi, Nicolas Jourdan, J. W. Maes, H. Bana, C. Zhu, R. Chukka, F. Sebaai, Kevin Vandersmissen, N. Heylen, D. Montero, S. Wang, K. D'Have, F. Schleicher, J. De Vos, Gerald Beyer, A. Miller, Eric Beyne:
Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c24]Francesco Lorenzelli
, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li
Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. ETS 2023: 1-6 - [c23]Francesco Lorenzelli
Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. ITC 2023: 151-158 - [c22]Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c21]Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits 2022: 284-285 - [c20]Rongmei Chen, Giuliano Sisto
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits 2022: 429-430 - 2021
- [j10]Kristof J. P. Jacobs
Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy. IEEE Trans. Instrum. Meas. 70: 1-7 (2021) - 2020
- [c19]Michele Stucchi, Ferenc Fodor, Erik Jan Marinissen:
Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios. ETS 2020: 1-6 - [c18]Olalla Varela Pedreira
Metal reliability mechanisms in Ruthenium interconnects. IRPS 2020: 1-7
2010 – 2019
- 2019
- [c17]Kris Croes, Veerle Simons, Sofie Beyne, Vladimir Cherman, Herman Oprins, Michele Stucchi, Philippe Absil, A. Glabman, Eric Wilcox:
Understanding EM-Degradation Mechanisms in Metal Heaters Used for Si Photonics Applications. IRPS 2019: 1-4 - 2018
- [c16]Yunlong Li, Michele Stucchi, Stefaan Van Huylenbroeck, Geert Van der Plas, Gerald Beyer, Eric Beyne
TSV process-induced MOS reliability degradation. IRPS 2018: 5 - [c15]Erik Jan Marinissen
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. ITC 2018: 1-10 - 2017
- [j9]Kristof J. P. Jacobs
Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices. Microelectron. Reliab. 76-77: 188-193 (2017) - 2016
- [j8]Kristof Croes, Joke De Messemaeker, Yunlong Li, Wei Guo, Olalla Varela Pedreira
Reliability Challenges Related to TSV Integration and 3-D Stacking. IEEE Des. Test 33(3): 37-45 (2016) - [c14]Stefaan Van Huylenbroeck, Yunlong Li, Michele Stucchi, Lieve Bogaerts, Joeri De Vos, Gerald Beyer, Eric Beyne
Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module. 3DIC 2016: 1-4 - 2015
- [c13]Ioannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare, Wim Dehaene:
Impact of interconnect multiple-patterning variability on SRAMs. DATE 2015: 609-612 - 2014
- [j7]Yunlong Li, Stefaan Van Huylenbroeck, Els Van Besien, Xiaoping Shi, Chen Wu, Michele Stucchi, Gerald Beyer, Eric Beyne
Reliability challenges for barrier/liner system in high aspect ratio through silicon vias. Microelectron. Reliab. 54(9-10): 1949-1952 (2014) - 2012
- [j6]Michele Stucchi, Dimitrios Velenis, Guruprasad Katti:
Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique. IEEE Trans. Instrum. Meas. 61(7): 1979-1990 (2012) - 2011
- [j5]Geert Van der Plas
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46(1): 293-307 (2011) - [j4]Herman Oprins, Adi Srinivasan
Fine grain thermal modeling and experimental validation of 3D-ICs. Microelectron. J. 42(4): 572-578 (2011) - 2010
- [c12]Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye
Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. CICC 2010: 1-4 - [c11]Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal:
3D integration: Circuit design, test, and reliability challenges. IOLTS 2010: 217 - [c10]Geert Van der Plas
Design issues and considerations for low-cost 3D TSV IC technology. ISSCC 2010: 148-149
2000 – 2009
- 2009
- [j3]Paul Marchal, Bruno Bougard, Guruprasad Katti, Michele Stucchi, Wim Dehaene, Antonis Papanikolaou, Diederik Verkest, Bart Swinnen, Eric Beyne
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot. Proc. IEEE 97(1): 96-107 (2009) - [c9]Jan Van Olmen, Jan Coenen, Wim Dehaene, Kristin De Meyer, Cedric Huyghebaert, Anne Jourdain, Guruprasad Katti, Abdelkarim Mercha, Michal Rakowski, Michele Stucchi, Youssef Travaly, Eric Beyne
3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). 3DIC 2009: 1-5 - [c8]Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen
Impact of 3D design choices on manufacturing cost. 3DIC 2009: 1-5 - 2008
- [c7]Jin Guo, Antonis Papanikolaou, Michele Stucchi, Kristof Croes, Zsolt Tokei, Francky Catthoor:
A tool flow for predicting system level timing failures due to interconnect reliability degradation. ACM Great Lakes Symposium on VLSI 2008: 291-296 - 2006
- [j2]Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene:
Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies. IEEE J. Solid State Circuits 41(11): 2577-2588 (2006) - [c6]Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene:
Statistically Aware SRAM Memory Array Design. ISQED 2006: 25-30 - [c5]Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex:
Impact of interconnect resistance increase on system performance of low power and high performance designs. SLIP 2006: 85-90 - 2004
- [c4]Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex:
Interconnect width selection for deep submicron designs using the table lookup method. SLIP 2004: 41-44 - 2003
- [c3]Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex:
Global interconnect trade-off for technology over memory modules to application level: case study. SLIP 2003: 125-132 - 2002
- [j1]Michele Stucchi, Karen Maex:
Frequency dependence in interline capacitance measurements. IEEE Trans. Instrum. Meas. 51(3): 537-543 (2002) - [c2]Hasan Ymeri, Bart Nauwelaers
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate. DATE 2002: 1113 - [c1]Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex:
Interconnect exploration for future wire dominated technologies. SLIP 2002: 105-106
Coauthor Index
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