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32nd VLSI Design 2019: Delhi, India
- 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019. IEEE 2019, ISBN 978-1-7281-0409-6
Track 1A: Embedded Systems - I
- Sumana Ghosh
, Soumyajit Dey, Pallab Dasgupta:
Synthesizing Performance-Aware (m, k)-Firm Control Execution Patterns Under Dropped Samples. 1-6 - Khushboo Rani, Hemangee K. Kapoor:
Write Variation Aware Non-volatile Buffers for On-Chip Interconnects. 7-12 - Dipika Deb
Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher. 13-18 - Somdip Dey
EdgeCoolingMode: An Agent Based Thermal Management Mechanism for DVFS Enabled Heterogeneous MPSoCs. 19-24
Track 1B: Analog/Mixed Signal - I
- Antroy Roy Chowdhury, Nijwm Wary
Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination. 25-30 - Japesh Vohra
Ultra Low Energy Reduced Switching DAC for SAR ADC. 31-35 - Abirmoya Santra, Qadeer A. Khan:
A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-Forward Compensation. 36-40 - Lalit Dani, Neeraj Mishra, Bulusu Anand:
MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques. 41-45
Track 1C: Digital Design - I
- Jinti Hazarika, Mohd. Tasleem Khan, Shaik Rafi Ahamed:
Low-Complexity Continuous-Flow Memory-Based FFT Architectures for Real-Valued Signals. 46-51 - Yudai Sakamoto, Shigeru Yamashita:
Reducing the Overhead of Stochastic Number Generators Without Increasing Error. 52-57 - Tripti Nirmalkar, Deepti Kanoujia, Kshitiz Varma:
Low Complexity & Improved Efficiency of Encoded Data Using Peres Gate in BWAR with Testable Feature. 58-63 - Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. 64-69
Track 2A: Security - I
- Richa Agrawal, Mike Borowczak
A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration. 70-75 - Ankush Srivastava, Prokash Ghosh
An Efficient Memory Zeroization Technique Under Side-Channel Attacks. 76-81 - Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal:
Two-Pattern ∆IDDQ Test for Recycled IC Detection. 82-87 - Maruthi Gillela, Vaclav Prenosil
Parallelization of Brute-Force Attack on MD5 Hash Algorithm on FPGA. 88-93
Track 2B: Test and Validation - I
- Pradeep Kumar Biswal, Santosh Biswas:
A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits. 94-99 - Aravind Krishnan Varadarajan, Michael Hsiao:
RTL Test Generation on Multi-core and Many-Core Architectures. 100-105 - Jaidev Shenoy, Kelly Ockunzzi, Virendra Singh, Kushal Kamal:
On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time. 106-111 - Vasudevan M. S, Santosh Biswas, Aryabartta Sahu
RSBST: A Rapid Software-Based Self-Test Methodology for Processor Testing. 112-117
Track 2C: RF Design
- Vipul Jain, Saurabh Kumar Gupta, Vishal Khatri, Gaurab Banerjee:
A 19.3-24.8 GHz Dual-Slope VCO in 65-nm CMOS for Automotive Radar Applications. 118-123 - Abhishek Srivastava
Analysis and Design of Low Phase Noise LC Oscillator for Sub-mW PLL-Free Biomedical Receivers. 124-129 - Anant Rungta, Kavindra Kandpal
IIP3 Improvement in Subthreshold LNAs Using Modified Derivative Superposition Technique for IoT Applications. 130-134 - Rohit Rothe, Rajesh Zele:
Enhanced IIP2 Chopper Stabilized Direct Conversion Mixer Architecture. 135-138
Track 3A: Power and Energy - I
- Pramod Kumar Bharti, Neelam Surana, Joycee Mekie:
Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications. 139-144 - Sanket Thakkar, Biswajit Mishra:
Ultra Low Power Digital Front-End for Single Lead ECG Acquisition. 145-150 - Sumanta Pyne:
Scheduling of Dual Supercapacitor for Longer Battery Lifetime in Systems with Power Gating. 151-156 - Shixiong Jiang, Sheena Ratnam Priya, Naveena Elango, James Clay, Ramalingam Sridhar:
An Energy Efficient In-Memory Computing Machine Learning Classifier Scheme. 157-162
Track 3B: CMOS Devices
- Amratansh Gupta
An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors. 163-167 - Manish Gupta, Abhinav Kranti:
Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless Transistors. 168-173 - Kiran Gopal, Avanish K:
Delay Skew Reduction in IO Glitch Filter. 174-178 - Madhuchhanda Brahma, Arnab Kabiraj
Insights on Anisotropic Dissipative Quantum Transport in n-Type Phosphorene MOSFET. 179-184
Track 3C: Emerging Tech - I
- T. Pravinraj
Modeling, Fabrication and Investigation of Mixing in Low-Cost Passive PDMS Micromixers. 185-190 - Tapalina Banerjee, Sudip Poddar
Design of Continuous-Flow Lab-on-Chip with 3D Microfluidic Network for Sample Preparation. 191-196 - Mohammed Shayan, Sukanta Bhattacharjee, Yong-Ak Song
Security Assessment of Microfluidic Fully-Programmable-Valve-Array Biochips. 197-202 - Anirban Bhattacharjee
Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits. 203-208
Track 4A: Intelligence on Silicon
- S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan:
UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs. 209-214 - Nandan Kumar Jha, Sparsh Mittal
The Ramifications of Making Deep Neural Networks Compact. 215-220 - Lavanya Maddisetti
Machine Learning Based Power Efficient Approximate 4: 2 Compressors for Imprecise Multipliers. 221-226 - Rajesh Kedia, Anupam Sobti, Mukund Rungta, Sarvesh Chandoliya, Akhil Soni, Anil Kumar Meena, Chrystle Myrna Lobo, Richa Verma, M. Balakrishnan, Chetan Arora:
MAVI: Mobility Assistant for Visually Impaired with Optional Use of Local and Cloud Resources. 227-232
Track 4B: Design Automation
- Satyabrata Dash, Sukanta Dey
RiverOpt: A Multiobjective Optimization Framework Based on Modified River Formation Dynamics Heuristic. 233-238 - Amartya Dutta, Riya Majumder, Debasis Dhal, Rajat Kumar Pal:
Structural and Behavioural Facets of Digital Microfluidic Biochips with Hexagonal-Electrode-Based Array. 239-244 - Subhash Jagadishchandra Patel, Rajesh Amratlal Thakker:
Parasitic-Aware Automatic Analog CMOS Circuit Design Environment. 245-250 - Sachin Kalburgi, Deven Gupta, Sampath Holi, Rohit Shetty, Shripad Annigeri, Shraddha H, Saroja V. Siddamal, Sujata Kotabagi, Nalini C. Iyer:
Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter. 251-256
Track 4C: Embedded Systems - II
- Swagata Mandal, Sreetama Sarkar, Ming Ming Wong, Anupam Chattopadhyay, Amlan Chakrabarti
Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA. 257-262 - Shivani Tripathy, Debiprasanna Sahoo
Multidimensional Grid Aware Address Prediction for GPGPU. 263-268 - Jinn-Pean Lin, Jing Lu, Jian Cai, Aviral Shrivastava
Efficient Heap Data Management on Software Managed Manycore Architectures. 269-274 - Martin Geier
In Situ Latency Monitoring for Heterogeneous Real-Time Systems. 275-280
Track 5A: IoT and CPS
- Vivek Kamalkant Parmar
Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN Applications. 281-286 - Kundan Kumar
A 75-µW 2.4 GHz Wake-up Receiver in 65-nm CMOS for Neonatal Healthcare Application. 287-292 - V. Prasanth
Perturbation Based Workload Augmentation for Comprehensive Functional Safety Analysis. 293-298 - Arijit Banerjee
A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications. 299-304
Track 5B: Analog /Mixed-Signal- II
- Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya:
A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC. 305-310 - Hari Shanker Gupta, Sanjeev Mehta, Maryam Shojaei Baghini
Large Dynamic Range Readout Integrated Circuit for Infrared Detectors. 311-316 - Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Riccardo Zurla
Current DAC Based -40dB PSRR Configurable Output LDO in BCD Technology. 317-322 - Maneesh Kumar Pandey, Mohit Goyal, Parul Sharma, Rohit Sharma:
Modeling and Characterization of VBUS Power Discharge for Embedded Superspeed USB Host/Devices. 323-328
Track 5C: Digital Design - II
- Rahul Shrestha, Pooja Bansal, Srikant Srinivasan
High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio. 329-334 - Ayan Palchaudhuri
VLSI Architectures for Jacobi Symbol Computation. 335-340 - Shubhanshu Gupta, Joycee Mekie:
Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop. 341-346 - Simmi M. Bose, Varsha S. Lalapura
k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics. 347-352
Track 6A: Security - II
- Arjun Singh Chauhan, Vineet Sahula
Novel Randomized & Biased Placement for FPGA Based Robust Random Number Generator with Enhanced Uniqueness. 353-358 - Amr Sayed-Ahmed, Jawad Haj-Yahya, Anupam Chattopadhyay:
SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection. 359-364 - Ghanshyam Bairwa, Souvik Mandal
Linear Approximation and Differential Attacks on Logic Locking Techniques. 365-370 - Sidhartha Sankar Rout
Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links. 371-376
Track 6B: Test and Validation - II
- Ramanuj Chouksey, Chandan Karfa
Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples. 377-382 - Manobennath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays. 383-388 - Binod Kumar, Masahiro Fujita, Virendra Singh:
A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. 389-394 - Shukla Banik, Suchismita Roy, Bibhash Sen:
Test Configuration Generation for Different FPGA Architectures for Application Independent Testing. 395-400
Track 6C: Emerging Tech - II
- Sanjay Vidhyadharan
An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices. 401-406 - Rakesh Das, Anupam Chattopadhyay, Hafizur Rahaman
Optimizing Quantum Circuits for Modular Exponentiation. 407-412 - Piyali Datta, Arpan Chakraborty, Rajat Kumar Pal:
A Capacity-Aware Wash Optimization for Contamination Removal in Programmable Microfluidic Biochip Devices. 413-418 - Ramakant Ramakant, Sanjay Vidhyadharan
Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications. 419-424
Track 7A: Embedded Systems - III
- Arijit Nath, Hemangee K. Kapoor:
Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches. 425-430 - Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Applying Modified Householder Transform to Kalman Filter. 431-436 - Vinay Kumar
Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler. 437-442 - Manoj Kumar Sharma, Umesh Chandra Lohani, Vivek Parmar
Design of an Optimized CMOS ELM Accelerator. 443-447
Track 7B: Digital Design - III
- Jayaraj U. Kidav, N. M. Sivamangai, Perumal M. Pillai, Sreejeesh S. G.
Design and Physical Implementation of Array Signal Processor ASIC for Sector Imaging Systems. 448-453 - Rahul Pathak, Raghavendra Kongari, Shankar Joshi:
Low Power Design Technique in Passive Tag to Reduce the EMD Noise for Reliable Communication with Reader. 454-458 - Krashna Nand Mishra, Ruchin Jain, Shailendra Sharad, Ravindra Shrivastava:
Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Periphery VDD Collapse in SRAMs. 459-463 - Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence. 464-469
Track 7C: Power and Energy - II
- Arun Joseph, Spandana Rachamalla, Shashidhar Reddy, Nagu R. Dhanwada:
Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis. 470-475 - Sanjay Moulik
HEART: A Heterogeneous Energy-Aware Real-Time Scheduler. 476-481 - Shubham Negi, Ashis Maity
Adaptive Fractional Open Circuit Voltage Method for Maximum Power Point Tracking in a Photovoltaic Panel. 482-487 - Mustafa M. Shihab, Vishwani D. Agrawal:
Energy Efficient Power Distribution on Many-Core SoC. 488-493
Interactive Presentation (IP) Poster Session
- Koushik Bharadwaj, Ashok Ray, Sushanta Bordoloi
Current Collapse Reduction Technique Using N-Doped Buffer Layer into the Bulk Region of a Gate Injection Transistor. 494-495 - Prajwal Sharma, Prashanthi K
Design and Analysis of a Minimally Invasive and ECG Controlled Ventricular Assistive Device. 496-497 - Vaishali H. Dhare, Usha Mehta
A Simple Synthesis Process for Combinational QCA Circuits: QSynthesizer. 498-499 - Naveen Murali G, Peddireddi Satya Vardhan, F. Lalchhandama, Kamalika Datta, Indranil Sengupta:
Mapping of Boolean Logic Functions onto 3D Memristor Crossbar. 500-501 - Jay Pathak
Stability Analysis of SRAM Designed Using In0.53Ga0.47As nFinFET with Underlap Region. 502-503 - Dinesh Rajasekharan, Amit Ranjan Trivedi, Yogesh Singh Chauhan
Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications. 504-505 - Navin Singhal, M. Santosh, S. C. Bose:
Reconfigurable Digital Logic Gate Based on Neuromorphic Approach. 506-507 - Vaibhav Agarwal, Sneh Saurabh
Realizing Boolean Functions Using Probabilistic Spin Logic (PSL). 508-509 - Varun Kumar Dwivedi, Meenakshi Didharia, Madhvi Sharma, Manoj Kumar Sharma:
Comparative Study of Analog Matching Structures in 28FDSOI. 510-511 - Debdut Biswas, Tarun Kanti Bhattacharyya:
A Model of Spurs for Delta-Sigma Fractional PLLs. 512-513 - Tathagato Bose, Kamalika Datta, Indranil Sengupta:
Exploiting Negative Control Lines and Nearest Neighbor for Improved Comparator Design. 514-515 - Nilotpal Chakraborty
Intelligent Scheduling of Smart Appliances in Energy Efficient Buildings: A Practical Approach. 516-517 - Yaswanth Krishna Yadav Danaboina, Pravanjan Samanta, Kamalika Datta, Indrajit Chakrabarti, Indranil Sengupta:
Design and Implementation of Threshold Logic Functions Using Memristors. 518-519 - Sana Mujeeb, Krishna Kanth Gowri Avalur:
A Transimpedance Amplifier with Improved PSRR at High Frequencies for EMI Robustness. 520-521 - Harshal Chapade, Rajesh Zele:
On-chip RF to DC Power Converter for Bio-Medical Applications. 522-524 - Karthik Narayanan, Vinayak Honkote, Dibyendu Ghosh, Swamy Baldev:
Energy Efficient Communication with Lossless Data Encoding for Swarm Robot Coordination. 525-526 - Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J.
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture. 527-528 - Ajay Homkar, Satish Patil, Lukman Rahumathulla, Raj Pawate, Sachin Ghanekar:
Extending STL BASOPs Used in 3GPP Codecs to Leverage Features of Modern DSP Architectures. 529-530 - Rajat Sadhukhan, Nilanjan Datta, Debdeep Mukhopadhyay:
A Machine Learning Based Approach to Predict Power Efficiency of S-Boxes. 531-532 - Gaurav Mishra
RF and RFID Based Object Identification and Navigation System for the Visually Impaired. 533-534 - Bikram Paul
Design and Implementation of Low-Power High-throughput PRNGs for Security Applications. 535-536 - Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri
Hardware Trojan Detection by Stimulating Transitions in Rare Nets. 537-538 - Timothy Dee, Ian Richardson, Akhilesh Tyagi:
Continuous Transparent Mobile Device Touchscreen Soft Keyboard Biometric Authentication. 539-540 - Indu Yadav
Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process. 541-542 - Yooseong Kim, Mohammad Khayatian, Aviral Shrivastava
WCET-Aware Stack Frame Management of Embedded Systems Using Scratchpad Memories. 543-544 - Shih-Chang Hung, Nick Iliev
Self-Organizing Maps-Based Flexible and High-Speed Packet Classification in Software Defined Networking. 545-546 - Ashish Kumar, Mohammad Aftab Alam, Gangaikondan S. Visweswaran:
A 0.8V V_MIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Repeated-Pulse Wordline Suppression Scheme. 547-548
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