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Hitesh Shrimali
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2020 – today
- 2024
- [j14]Saurabh Dhiman
, Hitesh Shrimali:
On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity. Integr. 97: 102175 (2024) - [j13]Saurabh Dhiman, Hitesh Shrimali:
Corrigendum to "On minimizing charge injection error using multi-dummy switches with enhanced linearity" [Integration volume 97 (2024) 102175]. Integr. 97: 102194 (2024) - [c24]Saurabh Dhiman, Hitesh Shrimali:
A 12.7 Bit Accurate and 5.3nJ·µV2·ns Comparator with Dynamic-cum-Body Bias Technique in SOI. ISCAS 2024: 1-5 - [c23]Azhar Yaseen N. J, Shivdeep, Sahil Sharma, Hitesh Shrimali, Devarshi Mrinal Das:
A 66dBΩ 5 GHz and 44.88 √Hz/(pA·pW) Inductorless TIA in 65 nm CMOS. MIXDES 2024: 55-60 - [c22]Sowmyashree S, Hitesh Shrimali:
An On-chip Thermoelectric Cooler Controller With Improved Driving Current of 2 A at 0.5 Ω Load. VLSID 2024: 129-134 - 2023
- [c21]Sowmyashree S, Hitesh Shrimali:
Fully Monolithic 1A Thermoelectric Cooler Controller with 90% Efficiency. ICECS 2023: 1-4 - [c20]Sowmyashree S, Hitesh Shrimali:
A Low Noise Bandgap Reference with 0.89 V Vref, 0.88 μVrms noise and 80 dB of PSRR. VLSID 2023: 1-6 - 2022
- [j12]Kumar Sambhav Pandey
Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations. IEEE Access 10: 56985-56995 (2022) - [j11]Muhammed Suhail Illikkal, Jai Narayan Tripathi
Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters. IEEE Access 10: 100172-100177 (2022) - [j10]B. Dinesh Kumar
Design and implementation of a second order PLL based frequency synthesizer for implantable medical devices. Integr. 86: 57-63 (2022) - 2021
- [j9]Ashish Joshi
Digitally Assisted Secondary Switch-and-Compare Technique for a SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2317-2321 (2021) - [c19]Gowtham Peringattu Kalarikkal, Rohit Goel, Hitesh Shrimali:
Design of CMOS Device Process Sensor in 28 nm FD-SOI with 2 % of Frequency Spread. ICECS 2021: 1-6 - [c18]B. Dinesh Kumar, Hitesh Shrimali, Nagarjuna Nallam:
A Low-Power Quadrature LC-Oscillator Using Core-and-Coupling Current-Reuse. ISCAS 2021: 1-5 - [c17]Navneet Gupta, Hitesh Shrimali, Adam Makosiej, Andrei Vladimirescu, Amara Amara:
Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC. MWSCAS 2021: 297-300 - [c16]Puneet Arora, Jai Narayan Tripathi
Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters due to Periodic Fluctuations. NEWCAS 2021: 1-4 - 2020
- [j8]Ashish Joshi, Hitesh Shrimali, Satinder K. Sharma:
Reduced switching mode for SAR ADCs: analysis and design of SAR A-to-D algorithm with periodic standby mode circuit components. IET Circuits Devices Syst. 14(5): 686-694 (2020) - [j7]B. Dinesh Kumar
Design of hybrid flash-SAR ADC using an inverter based comparator in 28 nm CMOS. Microelectron. J. 95 (2020) - [j6]Vijender Kumar Sharma
Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix. IEEE Open J. Circuits Syst. 1: 124-139 (2020) - [j5]Ashish Joshi
A Discrete-Time MOS Parametric Amplifier-Based Chopped Signal Demodulator. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2268-2279 (2020) - [c15]Saurabh Dhiman, Vijender Kumar Sharma, Hitesh Shrimali:
Design and Analysis of a Low PSIJ, Energy Efficient Bootstrapped Driver for Space Application. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j4]Jai Narayan Tripathi
A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers. IEEE Access 7: 125240-125252 (2019) - [c14]Saurabh Dhiman, Indu Yadav
Energy Efficient Bootstrapped Driver for a Particle Detector in 180 nm SOI Technology. APCCAS 2019: 273-276 - [c13]Kumar Sambhav Pandey, B. Dinesh Kumar
An Ultra-Fast Parallel Prefix Adder. ARITH 2019: 125-134 - [c12]Indu Yadav
Design of HV-CMOS Detectors in BCD Technology with Noise and Crosstalk Measurements. ICECS 2019: 398-401 - [c11]B. Dinesh Kumar
A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS. ISCAS 2019: 1-5 - [c10]Vijender Kumar Sharma
Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator. ISCAS 2019: 1-5 - [c9]Indu Yadav
Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process. VLSID 2019: 541-542 - 2018
- [c8]Ashish Joshi, Hitesh Shrimali, Satinder K. Sharma
The Capacitively Coupled Chopper Stabilized Amplifier with a DTPA based Demodulator. ISCAS 2018: 1-5 - [c7]Ankita Deo, Sumit K. Pandey, Ashish Joshi, Satinder K. Sharma, Hitesh Shrimali:
Design of a Third Order Butterworth Gm-C Filter for EEG Signal Detection Application. MIXDES 2018: 361-365 - 2017
- [j3]Ashish Joshi, Hitesh Shrimali, Satinder K. Sharma
Systematic design approach for a gain boosted telescopic OTA with cross-coupled capacitor. IET Circuits Devices Syst. 11(3): 225-231 (2017) - [c6]Hitesh Shrimali, Vijender Kumar Sharma
Nonlinear modeling and analysis of buck converter using volterra series. ICECS 2017: 222-226 - [c5]Vijender Kumar Sharma
Distortion analysis for a DC-DC buck converter. ISOCC 2017: 212-213 - 2016
- [c4]Ashish Joshi, Indu Yadav
The pole-zero doublet: A cascode operational amplifier with cross coupled capacitor. MWSCAS 2016: 1-4 - 2015
- [j2]Hitesh Shrimali, Shouri Chatterjee
A technique to linearize the discrete-time parametric amplifier. Microelectron. J. 46(11): 1033-1038 (2015) - 2014
- [c3]Hitesh Shrimali, Valentino Liberali
The start-up circuit for a low voltage bandgap reference. ICECS 2014: 92-95 - 2011
- [j1]Hitesh Shrimali, Shouri Chatterjee
Distortion Analysis of a Three-Terminal MOS-Based Discrete-Time Parametric Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 902-905 (2011) - [c2]Hitesh Shrimali, Shouri Chatterjee
11 GHz UGBW Op-amp with feed-forward compensation technique. ISCAS 2011: 17-20 - [c1]Hitesh Shrimali, Shouri Chatterjee
Third order harmonic cancellation technique for a parametric amplifier. ISCAS 2011: 1880-1883
Coauthor Index
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last updated on 2024-08-16 18:32 CEST by the dblp team
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