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Indrajit Chakrabarti
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2020 – today
- 2024
- [j49]Sivappriya Manivannan
, Rajat Subhra Chakraborty
Practical and Efficient PUF-Based Protocol for Authentication and Key Agreement in IoT. IEEE Embed. Syst. Lett. 16(2): 118-121 (2024) - [j48]Ashish Ranjan Shadangi
Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1285-1296 (2024) - [j47]Ashish Ranjan Shadangi
VLSI Architecture for Implementing OTFS. Wirel. Pers. Commun. 137(3): 1931-1944 (2024) - 2023
- [j46]Radhika V. Menon
Low complexity VLSI architecture for improved primal-dual support vector machine learning core. Microprocess. Microsystems 98: 104806 (2023) - [c28]Venkata Sreekanth Balijabudda, Kamalesh Acharya, Rajat Subhra Chakraborty, Indrajit Chakrabarti:
Theoretical Enumeration of Deployable Single-Output Strong PUF Instances Based on Uniformity and Uniqueness Constraints. ICISS 2023: 77-87 - 2022
- [j45]Anand Kumar Mukhopadhyay
Systematic realization of a fully connected deep and convolutional neural network architecture on a field programmable gate array. Comput. Electr. Eng. 97: 107628 (2022) - [j44]Ashish Singhadia
Efficient HEVC Encoding to Meet Bitrate and PSNR Requirements Using Parametric Modeling. Circuits Syst. Signal Process. 41(8): 4479-4511 (2022) - [j43]Anand Kumar Mukhopadhyay
Acoustic scene analysis using analog spiking neural network. Neuromorph. Comput. Eng. 2(4): 44003 (2022) - [i9]Suman Samui, Indrajit Chakrabarti, Soumya K. Ghosh:
Auditory Model based Phase-Aware Bayesian Spectral Amplitude Estimator for Single-Channel Speech Enhancement. CoRR abs/2202.04882 (2022) - 2021
- [j42]Prasad Nagabhushanamgari, Vikash Sehwag, Indrajit Chakrabarti, Santanu Chattopadhyay:
Embedding delay-based physical unclonable functions in networks-on-chip. IET Circuits Devices Syst. 15(1): 27-41 (2021) - [j41]Radhika V. Menon
High speed VLSI architecture for improved region based active contour segmentation technique. Integr. 77: 25-37 (2021) - [j40]Anand Kumar Mukhopadhyay, Atul Sharma, Indrajit Chakrabarti, Arindam Basu
Power-efficient Spike Sorting Scheme Using Analog Spiking Neural Network Classifier. ACM J. Emerg. Technol. Comput. Syst. 17(2): 12:1-12:29 (2021) - [j39]Ashish Singhadia
A fast integrated deblocking filter and sample-adaptive-offset parameter estimation architecture for HEVC. Microprocess. Microsystems 85: 104317 (2021) - [j38]Sudipta Bose
Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal. IEEE Trans. Circuits Syst. II Express Briefs 68(11): 3451-3455 (2021) - 2020
- [j37]Rohan Mukherjee, Indubu Gaana Vinod, Indrajit Chakrabarti, Pranab Kumar Dutta, Ajoy Kumar Ray:
Hexagon Based Compressed Diamond Algorithm for motion estimation and its dedicated VLSI system for HD videos. Expert Syst. Appl. 141 (2020) - [j36]Sudipta Bose
Framework for Automated Earthquake Event Detection Based on Denoising by Adaptive Filter. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3070-3083 (2020) - [j35]Ashish Singhadia
Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices. IEEE Trans. Consumer Electron. 66(3): 203-212 (2020) - [j34]Kota Naga Srinivasarao Batta
VLSI Architecture for Enhanced Approximate Message Passing Algorithm. IEEE Trans. Circuits Syst. Video Technol. 30(9): 3253-3267 (2020) - [j33]Shantharam Kalipatnapu
Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1283-1291 (2020)
2010 – 2019
- 2019
- [j32]Suman Samui
Time-frequency masking based supervised speech enhancement framework using fuzzy deep belief network. Appl. Soft Comput. 74: 583-602 (2019) - [j31]Shantharam Kalipatnapu
High-throughput Bit Flipping decoder for structured LDPC codes. IET Commun. 13(14): 2168-2172 (2019) - [j30]Ashish Singhadia
A Novel Algorithmic Approach for Efficient Realization of 2-D-DCT Architecture for HEVC. IEEE Trans. Consumer Electron. 65(3): 264-273 (2019) - [c27]Venkata Sreekanth Balijabudda, Dhruv Thapar, Pranesh Santikellur, Rajat Subhra Chakraborty, Indrajit Chakrabarti:
Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF. AsianHOST 2019: 1-6 - [c26]Bibhas Manna
Exploring Formaldehyde Sensing Capability of Noble Metal Decorated Reduced Graphene Oxide through First Principle Approach. IEEE SENSORS 2019: 1-4 - [c25]Yaswanth Krishna Yadav Danaboina, Pravanjan Samanta, Kamalika Datta, Indrajit Chakrabarti, Indranil Sengupta:
Design and Implementation of Threshold Logic Functions Using Memristors. VLSID 2019: 518-519 - [i8]N. Prasad, Navonil Chatterjee, Santanu Chattopadhyay, Indrajit Chakrabarti:
Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip. CoRR abs/1908.00289 (2019) - [i7]Anand Kumar Mukhopadhyay, Naligala Moses Prabhakar, Divya Lakshmi Duggisetty, Indrajit Chakrabarti, Mrigank Sharad:
Intelligent Wireless Sensor Nodes for Human Footstep Sound Classification for Security Application. CoRR abs/1912.10905 (2019) - 2018
- [j29]Baishik Biswas, Rohan Mukherjee, Indrajit Chakrabarti, Pranab Kumar Dutta, Ajoy Kumar Ray:
A High-Speed VLSI Architecture for Motion Estimation Using Modified Adaptive Rood Pattern Search Algorithm. Circuits Syst. Signal Process. 37(10): 4548-4567 (2018) - [j28]Rohan Mukherjee, Priyabrata Saha, Indrajit Chakrabarti, Pranab Kumar Dutta
Fast adaptive motion estimation algorithm and its efficient VLSI system for high definition videos. Expert Syst. Appl. 101: 159-175 (2018) - [j27]N. Prasad
Design and evaluation of ZMesh topology for on-chip interconnection networks. J. Parallel Distributed Comput. 113: 17-36 (2018) - [j26]Shiju Padmanabhan Puthenpurayil, Indrajit Chakrabarti, Rishi Virdi, Snehal Wasnik
VLSI architecture for fixed mesh based deformable motion estimation using ARPS algorithm. Microprocess. Microsystems 59: 92-102 (2018) - [j25]Indranil Hatai
A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 130-140 (2018) - [j24]Vikash Sehwag, N. Prasad
A Parallel Stochastic Number Generator With Bit Permutation Networks. IEEE Trans. Circuits Syst. II Express Briefs 65-II(2): 231-235 (2018) - [j23]N. Prasad
An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3543-3554 (2018) - [c24]Anand Kumar Mukhopadhyay, Indrajit Chakrabarti, Mrigank Sharad:
Classification of Hand Movements by Surface Myoelectric Signal Using Artificial-Spiking Neural Network Model. IEEE SENSORS 2018: 1-4 - [i6]Anand Kumar Mukhopadhyay, Indrajit Chakrabarti, Arindam Basu, Mrigank Sharad:
Power efficient Spiking Neural Network Classifier based on memristive crossbar network for spike sorting application. CoRR abs/1802.09047 (2018) - [i5]Suman Samui, Indrajit Chakrabarti, Soumya K. Ghosh:
Tensor-Train Long Short-Term Memory for Monaural Speech Enhancement. CoRR abs/1812.10095 (2018) - 2017
- [j22]Rohan Mukherjee, Baishik Biswas, Indrajit Chakrabarti, Pranab Kumar Dutta, Somnath Sengupta, Ajoy Kumar Ray:
Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of (512×512) Frames. Circuits Syst. Signal Process. 36(2): 640-657 (2017) - [j21]Suman Samui
FPGA Implementation of a Phase-Aware Single-Channel Speech Enhancement System. Circuits Syst. Signal Process. 36(11): 4688-4715 (2017) - [j20]Kota Naga Srinivasarao Batta, Vinay Chakravarthi Gogineni
A novel framework for compressed sensing based scalable video coding. Signal Process. Image Commun. 57: 183-196 (2017) - [j19]Debasish Bera
Another Look in the Analysis of Cooperative Spectrum Sensing over Nakagami-m Fading Channels. IEEE Trans. Wirel. Commun. 16(2): 856-871 (2017) - [c23]Anand Kumar Mukhopadhyay, Indrajit Chakrabarti, Mrigank Sharad:
Real-time digitized neural-spike storage scheme in multiple channels for biomedical applications. APSIPA 2017: 1430-1435 - [c22]Suman Samui
Deep Recurrent Neural Network Based Monaural Speech Separation Using Recurrent Temporal Restricted Boltzmann Machines. INTERSPEECH 2017: 3622-3626 - [c21]N. Prasad
Runtime mitigation of illegal packet request attacks in Networks-on-Chip. ISCAS 2017: 1-4 - [c20]Rohan Mukherjee, Anupam Banerjee, Indrajit Chakrabarti, Pranab Kumar Dutta, Ajoy Kumar Ray:
Efficient VLSI design of CAVLC decoder of H.264 for HD videos. ISED 2017: 1-4 - [c19]Suman Samui
Improving the Performance of Deep Learning Based Speech Enhancement System Using Fuzzy Restricted Boltzmann Machine. PReMI 2017: 534-542 - [c18]Mamata Panigrahy
Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder. VDAT 2017: 376-387 - 2016
- [j18]Mamata Panigrahy
Low-Delay Parallel Architecture for Fractal Image Compression. Circuits Syst. Signal Process. 35(3): 897-917 (2016) - [j17]Shiju Padmanabhan Puthenpurayil, Indrajit Chakrabarti, Rishi Virdi, Harsh Kaushik:
Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm. IET Circuits Devices Syst. 10(4): 309-316 (2016) - [j16]Suman Samui
Improved single channel phase-aware speech enhancement technique for low signal-to-noise ratio signal. IET Signal Process. 10(6): 641-650 (2016) - [j15]Rohan Mukherjee, Vikrant Mahajan, Anindya Sundar Dhar, Indrajit Chakrabarti:
High Performance VISI Design of Diamond Search Algorithm for Fast Motion Estimation. J. Circuits Syst. Comput. 25(9): 1650114:1-1650114:16 (2016) - [j14]Rohan Mukherjee, Baishik Biswas, Indrajit Chakrabarti, Pranab Kumar Dutta, Ajoy Kumar Ray:
Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos. Microprocess. Microsystems 45: 105-114 (2016) - [j13]Debasish Bera, Indrajit Chakrabarti, Sant Sharan Pathak:
Modelling of Cooperative Spectrum Sensing over Rayleigh Fading Without CSI in Cognitive Radio Networks. Wirel. Pers. Commun. 86(3): 1281-1297 (2016) - [c17]Sandip Das, Suvra Sekhar Das, Indrajit Chakrabarti:
Hardware implementation of MIL-STD-1553 protocol over OFDMA-PHY based wireless high data rate avionics systems. ANTS 2016: 1-6 - [c16]Suman Samui
Two-Stage Temporal Processing for Single-Channel Speech Enhancement. INTERSPEECH 2016: 3723-3727 - [c15]Suman Samui, Indrajit Chakrabarti, Soumya Kanti Ghosh:
Global soft decision based speech enhancement using voiced-unvoiced uncertainty and harmonic phase decomposition technique. SPCOM 2016: 1-5 - [i4]Kota Naga Srinivasarao Batta, Vinay Chakravarthi Gogineni, Subrahmanyam Mula, Indrajit Chakrabarti:
VLSI Friendly Framework for Scalable Video Coding based on Compressed Sensing. CoRR abs/1602.07453 (2016) - 2015
- [b1]Indrajit Chakrabarti, Kota Naga Srinivasarao Batta, Sumit Kumar Chatterjee:
Motion Estimation for Video Coding - Efficient Algorithms and Architectures. Studies in Computational Intelligence 590, Springer 2015, ISBN 978-3-319-14375-0, pp. 1-111 - [j12]Rohan Mukherjee, Keyur Sheth, Anindya Sundar Dhar, Indrajit Chakrabarti, Somnath Sengupta:
High Performance VLSI Architecture for Three-Step Search Algorithm. Circuits Syst. Signal Process. 34(5): 1595-1612 (2015) - [j11]Kota Naga Srinivasarao Batta, Indrajit Chakrabarti, Mohammad Nawaz Ahmad:
High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter. IET Circuits Devices Syst. 9(5): 377-383 (2015) - [j10]Baishik Biswas, Rohan Mukherjee, Indrajit Chakrabarti:
Efficient architecture of adaptive rood pattern search technique for fast motion estimation. Microprocess. Microsystems 39(3): 200-209 (2015) - [j9]N. Prasad
Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip. Microprocess. Microsystems 39(8): 741-751 (2015) - [j8]Indranil Hatai
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1071-1080 (2015) - [j7]Indranil Hatai
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1150-1154 (2015) - [c14]Suman Samui
A phase-aware single channel speech enhancement technique using separate bayesian estimators for voiced and unvoiced regions with digital hearing aid application. HealthCom 2015: 336-341 - [c13]N. Prasad
ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms. iNIS 2015: 146-151 - [c12]Sandip Das, Indrajit Chakrabarti, Suvra Sekhar Das:
Hardware implementation of Frequency Domain Link Adaptation for OFDMA based systems. NCC 2015: 1-6 - [c11]Subhomoy Bhattacharyya, Indrajit Chakrabarti, Maheshkumar H. Kolekar:
Complexity assisted consistent quality rate control for high resolution H.264 video conferencing. NCVPRIPG 2015: 1-4 - [c10]Radhika V. Menon, Poulami Raha, Shweta Kothari, Sumit Chakraborty, Indrajit Chakrabarti, Rezaul Karim:
Automated detection and classification of mass from breast ultrasound images. NCVPRIPG 2015: 1-4 - [i3]Kota Naga Srinivasarao Batta, Indrajit Chakrabarti:
Hardware Implementation of Compressed Sensing based Low Complex Video Encoder. CoRR abs/1509.03836 (2015) - [i2]Kota Naga Srinivasarao Batta, Indrajit Chakrabarti:
High Speed VLSI Architecture for 3-D Discrete Wavelet Transform. CoRR abs/1509.04268 (2015) - 2014
- [c9]Debasish Bera, Shobhit Maheshwari, Indrajit Chakrabarti, Sant Saran Pathak:
Decentralized cooperative spectrum sensing in cognitive radio without fusion centre. NCC 2014: 1-5 - [c8]Mamata Panigrahy
VLSI design of fast fractal image encoder. VDAT 2014: 1-2 - 2013
- [c7]Indranil Hatai
Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter. IPDPS Workshops 2013: 247-251 - [c6]Sumit Kumar Chatterjee, Indrajit Chakrabarti:
Algorithm and architecture for quarter pixel motion estimation for H.264/AVC. NCVPRIPG 2013: 1-4 - [c5]R. Mukherjee, Vikrant Mahajan, Indrajit Chakrabarti, S. Sengupta:
High performance VLSI implementation of Context-based Adaptive Variable Length Coding (CAVLC) for H.264 encoder. NCVPRIPG 2013: 1-4 - 2012
- [j6]Shaikh Montajul Karim, Indrajit Chakrabarti:
High-throughput turbo decoder using pipelined parallel architecture and collision-free interleaver. IET Commun. 6(11): 1416-1424 (2012) - 2011
- [j5]Indranil Hatai
A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation. Int. J. Reconfigurable Comput. 2011: 342532:1-342532:10 (2011) - [j4]Sumit Kumar Chatterjee, Indrajit Chakrabarti:
Power efficient motion estimation algorithm and architecture based on pixel truncation. IEEE Trans. Consumer Electron. 57(4): 1782-1790 (2011) - 2010
- [j3]Shaikh Montajul Karim, Indrajit Chakrabarti:
An improved low-power high-throughput log-MAP turbo decoder. IEEE Trans. Consumer Electron. 56(2): 450-457 (2010) - [j2]Sumit Kumar Chatterjee, Indrajit Chakrabarti:
Low power VLSI architectures for one bit transformation based fast motion estimation. IEEE Trans. Consumer Electron. 56(4): 2652-2660 (2010) - [c4]Jaydeb Bhaumik, Dipanwita Roy Chowdhury, Indrajit Chakrabarti:
Null Boundary 90/150 Cellular Automata for Multi-byte Error Correcting Code. ACRI 2010: 231-240 - [i1]Indranil Hatai, Indrajit Chakrabarti:
Multi-standard programmable baseband modulator for next generation wireless communication. CoRR abs/1009.6132 (2010)
2000 – 2009
- 2009
- [j1]Kalyan Goswami, Indrajit Chakrabarti, Shamik Sural
A probabilistic adaptive algorithm for constructing hierarchical meshes. IEEE Trans. Consumer Electron. 55(3): 1690-1698 (2009) - 2008
- [c3]Jaydeb Bhaumik, Dipanwita Roy Chowdhury, Indrajit Chakrabarti:
An Improved Double Byte Error Correcting Code Using Cellular Automata. ACRI 2008: 463-470 - [c2]Kota Naga Srinivasarao Batta, Indrajit Chakrabarti:
A Parallel Architecture for Successive Elimination Block Matching Algorithm. ICVGIP 2008: 226-231 - [c1]Tenugu Suman, Sumit Kumar Chatterjee, Indrajit Chakrabarti:
High Speed and Memory Efficient Parallel Bit Plane Coding Architecture for JPEG2000. ICVGIP 2008: 232-237
Coauthor Index
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