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VTS 1991: Atlantic City, NJ, USA
- 9th IEEE VLSI Test Symposium (VTS'91), 15-17 Apr 1991, Atlantic City, NJ, USA. IEEE Computer Society 1991
- Harald Gundlach, Bernd K. Koch, Klaus D. Müller-Glaser:
Using target faults to achieve a minimized partial scan path. 4-9 - R. P. van Riessen, Hans G. Kerkhoff, J. M. J. Janssen:
A design-for-testability expert system for silicon compilers. 10-15 - Susheel J. Chandra, Tushar Gheewala, Hector R. Sucar, George Swan:
Use of CrossCheck test technology in practical applications. 16-21 - Srinivas Devadas, Kurt Keutzer, Abhijit Ghosh:
Recent progress in synthesis for testability. 22-29 - Paul S. Levy:
Power-down integrated circuit built-in self-test structures. 30-33 - Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer:
A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing. 34-39 - K. El. Maadani, Jean Claude Geffroy:
Identification of structured automata for test evaluation. 40-46 - Hee Yong Youn:
Compact testing with intermediate signature analysis. 47-52 - Rochit Rajsuman:
An analysis of feedback bridging faults in MOS VLSI. 53-58 - Benjamin R. Epstein, Steven R. Miller, Martin H. Czigler, David R. Gray:
Linear microcircuit fault modeling and detection. 59-61 - Stanford S. Guillory, Daniel G. Saab, Andrew T. Yang:
Fault modeling and testing of self-timed circuits. 62-66 - Mani Soma:
Probabilistic measures of fault equivalence in mixed-signal systems. 67-70 - Stephen L. Dingle, Luke D. Lacroix, Peter A. Twombly:
The advantages of boundary-scan testing. 71-77 - Steven F. Oakland:
Combining IEEE Standard 1149.1 with reduced-pin-count component test. 78-84 - David S. Karpenske:
Interconnect verification of multichip modules using boundary scan. 85-91 - Robert Cortez, R. Dandapani, Mike Yeager:
Issues of integrating the IEEE Std 1149.1 into a gate array. 92-97 - Nikolaos G. Bourbakis, Chittoor V. Ramamoorthy:
Specifications for the development of an expert tool for the automatic optical understanding of electronic circuits: VLSI reverse engineering. 98-103 - Waisum Wong, Juin J. Liou, Jiann-Shiun Yuan, David M. Wu:
Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits. 104-108 - Ashok K. Sharma:
VLSI procurement and qualification: NASA/GSFC experience, issues and concerns. 109-113 - E. Weis, E. Kinsbron, G. Chanoch, M. Snyder:
High accelerated lifetime test methods and procedures for VLSI microcircuit interconnection line certification. 114-117 - George M. Belansek, Peter Loomis, Fred J. Towler, Charles Warner, Donald Wheeler:
A multilayered ceramic (MLC) interface design for 125+MHz performance wafer probing [of SRAMs]. 118-122 - M. C. Kohalmy:
An adaptive device impedance matching circuit. 123-127 - Michael Chowanetz, Claus Kuntzsch, Werner Wolz:
Aspects on integration of high-speed multiplexers and demultiplexers in VLSI test systems. 128-133 - Richard M. Smyczynski, Kevin Brennan:
A software system architecture for testing multiple part number wafers. 134-136 - Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya, Juney Park:
An analysis and testing of operation induced faults in MOS VLSI. 137-142 - Bruno Ciciani:
Modeling the effects of imperfect production testing on reconfigurable VLSI chips. 143-148 - H.-D. Oberle, M. Maue, Peter Muhmenthaler:
Enhanced fault modeling for DRAM test and analysis. 149-154 - David Sweetman:
Guardbanding VLSI EEPROM test programs. 155-160 - Wolfgang Hahn, Michael Gössel:
Pseudoduplication of floating-point addition. A method of compiler generated checking of permanent hardware faults. 161-165 - Parag K. Lala, Fadi Y. Busaba, K. C. Yarlagadda:
An approach for designing self-checking logic using residue codes. 166-171 - Nageswara S. V. Rao, Shunichi Toida:
On polynomial-time testable classes of combinational circuits. 172-177 - Michal Cutler, Stephen Y. H. Su, Mingshien Wang:
Distributed self-diagnosis of VLSI mesh array processors. 178-186 - Paul G. Ryan, Shishpal Rawat, W. Kent Fuchs:
Automated diagnosis of VLSI failures. 187-192 - Scott F. Midkiff, S. Wayne Bollinger:
Circuit-level classification and testability analysis for CMOS faults. 193-198 - Angus Wu
, Tai-Shan Lin, C. Tseng, Jack L. Meador:
Neural network diagnosis of IC faults. 199-203 - Hede Ma, Ying Liu:
Design for diagnosable multiple-output digital systems. 204-209 - Mark A. Heap, William A. Rogers, William B. Burns:
STarS: a target switching algorithm for sequential test generation. 210-215 - Warren H. Debany Jr.:
Measuring the coverage of node shorts by internal access methods. 215-220 - Nikolaus Gouders, Reinhard Kaibel:
Test generation techniques for sequential circuits. 221-226 - Chung Ho Chen, N. L. Soong:
A statistical model for fault coverage analysis. 227-232 - Jiann-Shiun Yuan, Juin J. Liou, David M. Wu:
Testing the impact of process defects on ECL power-delay performance. 233-238 - David M. Wu:
An optimized delay testing technique for LSSD-based VLSI logic circuits. 239-248 - Christophe Gauthron:
At-speed testing of ASICs. 249-253 - Kyle G. Welch, James A. Monzel, Donald S. Kent, Donald W. Joseph:
Delay testing and failure analysis of ECL logic with embedded memories. 254-259 - Reda H. Seireg
Comparison between the dynamic behavior of maximum length and cyclic shift registers. 260-264 - Wilfred Hartmann, Cordt-Wilhem Starke:
Testing of VLSI CMOS System/390 processor at card and system level. 265-270 - Sheng Feng, Yashwant K. Malaiya:
Evaluation of detectability in BIST environment. 271-276 - Prawat Nagvajara, Mark G. Karpovsky, Lev B. Levitin:
Efficient test generation for built-in self-test boundary-scan template. 277-284 - Steven D. McEuen:
IDDq benefits [digital CMOS testing]. 285-290 - Yashwant K. Malaiya, Anura P. Jayasumana, Qiao Tong, Sankaran M. Menon:
Enhancement of resolution in supply current based testing for large ICs. 291-296 - F. Joel Ferguson, Tracy Larrabee:
Test pattern generation for current testable faults in static CMOS circuits. 297-302 - Kuen-Jong Lee, Melvin A. Breuer:
Constraints for using IDDQ testing to detect CMOS bridging faults. 303-308
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