This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC.

Abstract: This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC.

This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC.

This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC.

framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self- testable macros automatically.

A design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC and together with an efficient ...

R. P. van Riessen, Hans G. Kerkhoff, J. M. J. Janssen: A design-for-testability expert system for silicon compilers. VTS 1991: 10-15. manage site settings.

A design-for-testability expert system for silicon compilers. van Riessen R.P., Kerkhoff H.G., Janssen J.M.. Expand. Publication type: Proceedings Article.

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This approach has been developed further by integrating the expert system into a silicon compiler environment which ensures that the circuit is testable by ...