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"An optimized delay testing technique for LSSD-based VLSI logic circuits."

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David M. Wu (1991)

Dagstuhl

Trier

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DOI: 10.1109/VTEST.1991.208165

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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David M. Wu:
An optimized delay testing technique for LSSD-based VLSI logic circuits. VTS 1991: 239-248

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