default search action
ISQED 2007: San Jose, California, USA
- 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA. IEEE Computer Society 2007, ISBN 978-0-7695-2795-6
Tutorials
- Gerhard Knoblinger, James W. Tschanz, Marcal Pol:
SUB-45nm Technology and Design Challenges. 3 - Gerhard Knoblinger:
Multi-Gate MOSFET Design. 3 - James W. Tschanz:
SUB 45nm Low Power Design Challenges. 4 - Marcal Pol:
Self-Adaptive Systems to Drive out the Nano-Scale Devil. 4 - Srikanth Venkataraman, Nagesh Nagapalli, Lech Józwiak:
Quality Driven Manufacturing and SOC Designs. 5 - Srikanth Venkataraman:
DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield. 5 - Nagesh Nagapalli:
DFT and Test: Ensuring Product Quality. 5 - Lech Józwiak:
Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCs. 6
Evening Panel Discussion EP1
- Resve A. Saleh, Pallab K. Chatterjee, Ivan Pesic, Robbert Dobkins, Mike Smayling, Joseph Sawicki:
DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering? 7-8
Plenary Session 1P
- Jeong-Taek Kong:
Tipping Point for New Design Technologies: DFM, Low Power and ESL. 9-14
Session 1A: Design for Manufacturing
- Duane S. Boning, Karthik Balakrishnan, Hong Cai, Nigel Drego, Ali Farahanchi, Karen Gettings, Daihyun Lim, Ajay Somani, Hayden Taylor, Daniel Truque, Xiaolin Xie:
Variation. 15-20 - Takashi Sato
, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa
A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. 21-26 - Rajani Kuchipudi, Hamid Mahmoodi
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS. 27-32 - Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif:
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. 33-40
Session 1B: Device and Circuit Reliability
- Rakesh Vattikonda, Yansheng Luo, Alex Gyure, Xiaoning Qi, Sam C. Lo, Mahmoud Shahram, Yu Cao, Kishore Singhal, Dino Toffolon:
A New Simulation Method for NBTI Analysis in SPICE Environment. 41-46 - Xiangning Yang, Kewal K. Saluja:
Combating NBTI Degradation via Gate Sizing. 47-52 - Benoit Dubois, Jean-Baptiste Kammerer, Luc Hébrard, Francis Braun:
Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability. 53-58 - Aram Shin, Sang Jun Hwang, Seung Woo Yu, Man Young Sung:
A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays. 59-66
Session 1C: Power and Thermal Management
- Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud:
Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. 67-72 - Sherif A. Tawfik, Volkan Kursun
Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew. 73-78 - Weihuang Wang, Gwan Choi:
Speculative Energy Scheduling for LDPC Decoding. 79-84 - Kanak Agarwal, Kevin J. Nowka
Dynamic Power Management by Combination of Dual Static Supply Voltages. 85-92
Session 1D: Analog and Mixed Signal Design
- Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner
Low Voltage Buffered Bandgap Reference. 93-97 - Pengfei Li, Rizwan Bashirullah:
A DLL Based Multiphase Hysteretic DC-DC Converter. 98-101 - Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan
Statistical Timing Analysis Considering Spatial Correlations. 102-107 - Liang Rong, Martin Gustafsson, Ana Rusu
Systematic Design of a Flash ADC for UWB Applications. 108-114
Luncheon Speech
- Thomas W. Williams:
EDA to the Rescue of the Silicon Roadmap. 115-118
Session 2A: Quality and Reliability
- Arthur Nieuwoudt, Yehia Massoud:
Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions. 119-126 - Tamer Cakici, Keejong Kim, Kaushik Roy:
FinFET Based SRAM Design for Low Standby Power Applications. 127-132 - Asha Balijepalli, Joseph Ervin, Yu Cao, Trevor Thornton
Compact Modeling of a PD SOI MESFET for Wide Temperature Designs. 133-138 - Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie:
Modeling of PMOS NBTI Effect Considering Temperature Variation. 139-144 - Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong:
Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. 145-152
Session 2B: Advances in Timing and Power in Physical Design
- Ahmed Youssef, Tor Myklebust, Mohab Anis, Mohamed I. Elmasry:
A Low-Power Multi-Pin Maze Routing Methodology. 153-158 - Pei-Yu Huang, Huan-Yu Chou, Yu-Min Lee:
An Aggregation-Based Algebraic Multigrid Method for Power Grid Analysis. 159-164 - Gustavo R. Wilke, Rajeev Murgai:
Design and Analysis of "Tree+Local Meshes" Clock Architecture. 165-170 - Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi:
An Efficient Algorithm for RLC Buffer Insertion. 171-175 - Nahmsuk Oh, Alireza Kasnavi, Peivand F. Tehrani:
Fast Crosstalk Repair by Quick Timing Change Estimation. 176-184
Session 2C: Power-Aware System Design Methodologies
- Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson:
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. 185-191 - Amin Khajeh Djahromi, Ahmed M. Eltawil
Cross Layer Error Exploitation for Aggressive Voltage Scaling. 192-197 - Hwisung Jung, Massoud Pedram:
A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking Systems. 198-203 - Yongpan Liu, Huazhong Yang, Robert P. Dick, Hui Wang, Li Shang:
Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems. 204-209 - Foad Dabiri, Roozbeh Jafari, Ani Nahapetian, Majid Sarrafzadeh:
A Unified Optimal Voltage Selection Methodology for Low-Power Systems. 210-218
Session 2D: Poster Papers
- Charbel J. Akl, Magdy A. Bayoumi:
Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion. 219-224 - Bi Yuan, Yi Zhang, Lili He:
A 8b 10Ms/s Low Power Pipelined A/D Converter. 225-228 - Yamei Li, Lili He:
First-Order Continuous-Time Sigma-Delta Modulator. 229-232 - Yokesh Kumar, Prosenjit Gupta:
Reducing EPL Alignment Errors for Large VLSI Layouts. 233-238 - Zhiyu Liu, Volkan Kursun
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS. 239-244 - Taeyong Je, Yungseon Eo:
Efficient Signal Integrity Verification of Multi-Coupled Transmission Lines with Asynchronously Switching Non-Linear Drivers. 245-250 - Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. 251-256 - Bao Liu:
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations. 257-262 - Xudong Niu, Yan Song, Bo Li, Wei Bian, Yadong Tao, Feng Liu, Jinhua Hu, Yu Chen, Frank He:
Tests on Symmetry and Continuity between BSIM4 and BSIM5. 263-268 - Naiyong Jin, Taoyong Ni:
Interface Specification Assurance Methods. 269-274 - Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan
Multi-Dimensional Circuit and Micro-Architecture Level Optimization. 275-280 - Nigel Drego, Anantha P. Chandrakasan, Duane S. Boning:
A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays. 281-286 - Rishi Bhooshan:
Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits. 287-292 - Alfred L. Crouch, Phil Burlison, Dennis J. Ciplickas:
Processing High Volume Scan Test Results for Yield Learning. 293-298 - Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. 299-304 - David Rennie, Manoj Sachdev:
Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits. 305-310 - Daniela De Venuto
Inductive Fault Analysis for Test and Diagnosis of DNA Sensor Arrays. 311-316 - Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy:
Fine-Grained Redundancy in Adders. 317-321 - Abby A. Ilumoka, Hong Lang Tan:
MEMS Failure Probability Prediction and Quality Enhancement Using Neural Networks. 322-326 - Venkataraman Mahalingam, N. Ranganathan:
Variation Aware Timing Based Placement Using Fuzzy Programming. 327-332 - Amol Mupid, Madhu Mutyam
Variation Analysis of CAM Cells. 333-338 - Qi Lin, Mei Ma, Tony Vo, Jenny Fan, Xin Wu, Richard Li, Xiao-Yu Li:
Design-for-Manufacture for Multi Gate Oxide CMOS Process. 339-343 - Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho:
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure. 344-349 - Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong:
Power Delivery Aware Floorplanning for Voltage Island Designs. 350-355 - Boyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy:
Passive Modeling of Interconnects by Waveform Shaping. 356-361 - Kaijian Shi, Zhian Lin, Yi-Min Jiang:
A Power Network Synthesis Method for Industrial Power Gating Designs. 362-367 - Yuan Cai, Sudhakar M. Reddy, Bashir M. Al-Hashimi:
Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint. 368-373 - Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato
Challenges in Evaluations for a Typical-Case Design Methodology. 374-379 - Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew:
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. 380-385 - Xiaofang Wang, Sotirios G. Ziavras
Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors. 386-391 - Gautam Kumar Singh, Santosh Kumar Panigrahi:
A High Frequency PWM Controller in HV Bi-CMOS Process Considering SOI Self-Heating. 392-397 - Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan:
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. 398-403 - Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham:
Built-In Test of RF Mixers Using RF Amplitude Detectors. 404-409 - Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas:
Glitch Control with Dynamic Receiver Threshold Adjustment. 410-415 - Yong Sin Kim, Sung-Mo Kang:
Programmable High Speed Multi-Level Simultaneous Bidirectional I/O. 416-419 - Manoj Kumar Goparaju, Spyros Tragoudas:
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations. 420-425 - Kumar Yelamarthi
Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. 426-431 - Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud:
Wavelet-Based Passivity Preserving Model Order Reduction for Wideband Interconnect Characterization. 432-437 - Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh:
System Level Estimation of Interconnect Length in the Presence of IP Blocks. 438-443 - Rasit Onur Topaloglu
Energy-Minimization Model for Fill Synthesis. 444-451 - Santosh Shah, Arani Sinha, Li Song, Narain D. Arora:
On-Chip Inductance in X Architecture Enabled Design. 452-457 - Ashok Narasimhan, Ramalingam Sridhar:
Impact of Variability on Clock Skew in H-tree Clock Networks. 458-466
Session 3A: Electrical Quality
- Andrew B. Kahng, Rasit Onur Topaloglu
A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances. 467-474 - Jeong-Yeol Kim, Ho-Soon Shin, Jong-Bae Lee, Moon-Hyun Yoo, Jeong-Taek Kong:
SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design. 475-480 - Jun Zou, Daniel Mueller
Pareto-Front Computation and Automatic Sizing of CPPLLs. 481-486 - Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco:
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. 487-494
Session 3B: Analog and RF Testing
- Joonsung Park, Hongjoong Shin, Jacob A. Abraham:
Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model. 495-500 - Amit Laknaur, Rui Xiao, Sai Raghuram Durbha, Haibo Wang:
Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications. 501-506 - Hyunsik Kim, Yungseon Eo:
High-Frequency-Measurement-Based Frequency-Variant Transmission Line Characterization and Circuit Modeling for Accurate Signal Integrity Verification. 507-512 - Guo Yu, Peng Li, Wei Dong:
Achieving Low-Cost Linearity Test and Diagnosis of Sigma Delta ADCs via Frequency-Domain Nonlinear Analysis and Macromodeling. 513-518 - Daniela De Venuto
Fully Digital Optimized Testing and Calibration Technique for Sigma Delta ADC's. 519-526
Session 3C: Low Power Circuits
- Youngsoo Shin, Hyung-Ock Kim:
Cell-Based Semicustom Design of Zigzag Power Gating Circuits. 527-532 - Byunghee Choi, Youngsoo Shin:
Lookup Table-Based Adaptive Body Biasing of Multiple Macros. 533-538 - Toshinori Sato
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM. 539-544 - Jaydeep P. Kulkarni, Kaushik Roy:
A High Performance, Scalable Multiplexed Keeper Technique. 545-549 - Andrew B. Kahng, Sherief Reda, Puneet Sharma:
On-Line Adjustable Buffering for Runtime Power Reduction. 550-555
Plenary Session 2P
- Marc Duranton:
Programmable Engines for Embedded Systems: The New Challenges. 556-557 - Marc Derbey:
Soft-Errors Phenomenon Impacts on Design for Reliability Technologies. 558-559 - Joseph Sawicki:
Forging Tighter Connections Between Design and Manufacturing in the Nanometer Age. 560-566
Session 4A: Package Circuit Co-Design
- Dongkeun Oh
3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method. 567-572 - Eunseok Song, Heeseok Lee, Jungtae Lee, Woojin Jin, Kiwon Choi, Sa-Yoon Kang:
Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design. 573-579 - Syed M. Alam, Robert E. Jones, Shahid Rauf, Ritwik Chatterjee:
Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology. 580-585 - Juan Pablo Martinez Brito, Hamilton Klimach, Sergio Bampi
A Design Methodology for Matching Improvement in Bandgap References. 586-594
Session 4B: High Level Optimization
- David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs. 595-601 - Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang:
Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis. 602-606 - Dimitri Kagaris, Themistoklis Haniotakis:
Transistor-Level Synthesis for Low-Power Applications. 607-612 - Marc Boule, Jean-Samuel Chenard, Zeljko Zilic:
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. 613-620
Session 4C: Interconnects and Power Grids
- Jae-sun Seo, Prashant Singh, Dennis Sylvester, David T. Blaauw:
Self-Time Regenerators for High-Speed and Low-Power Interconnect. 621-626 - Hong Li, Jitesh Jain, Venkataramanan Balakrishnan
Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization. 627-632 - Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan, Hao Yu:
General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits. 633-638 - Mini Nanua, David T. Blaauw:
Investigating Crosstalk in Sub-Threshold Circuits. 639-646
Session 4D: Parametric Variations in Design
- Smruti R. Sarangi, Brian Greskamp, Josep Torrellas:
A Model for Timing Errors in Processors with Parameter Variation. 647-654 - Mosin Mondal, Kartik Mohanram, Yehia Massoud:
Parameter-Variation-Aware Analysis for Noise Robustness. 655-659 - Kenichi Shinkai, Masanori Hashimoto
Future Prediction of Self-Heating in Short Intra-Block Wires. 660-665 - Javid Jaffari, Mohab Anis:
Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model. 666-671
Luncheon Panel Discussion LP2
- Jacques Benkoski, Michelle Clancy, Shankar Krishnamoorthy, David Holt, Ravi Subramanian, Clive Bittlestone, Tsuyoshi Yamamoto, Andrew Kanhg:
Do Digital Design and Variability Mix like Oil and Water? 672-676
Session 5A: DFM Statistics
- Ayhan A. Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, Long-Ching Yeh:
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization. 677-684 - Amith Singhee, Rob A. Rutenbar
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis. 685-692 - Robert C. Aitken:
Defect or Variation? Characterizing Standard Cell Behavior at 90nm and below. 693-698 - Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski:
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology. 699-702 - Uthman Alsaiari, Resve A. Saleh:
Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. 703-710
Session 5B: Timing Test and Reliability
- Rajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham:
Small-Delay Defect Detection in the Presence of Process Variations. 711-716 - Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov:
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture. 717-722 - Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
On Accelerating Soft-Error Detection by Targeted Pattern Generation. 723-728 - Edward Flanigan, Spyros Tragoudas:
Enhanced Identification of Strong Robustly Testable Paths. 729-736
Session 5C: Variation Analysis and Design
- Zhuo Feng, Guo Yu, Peng Li:
Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension Reduction. 737-742 - Ning Lu, Judy H. McCullen:
Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance. 743-748 - Yang Liu, Tong Zhang, Jiang Hu:
Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. 749-754 - Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. 755-760 - Ali Dasdan, Jinfeng Liu, Sridhar Tirumala, Kayhan Küçükçakar:
Designing and Validating Process-Variation-Aware Cell Libraries. 761-770
Session 5D: Lithography and OPC
- Jianliang Li, Qiliang Yan, Lawrence S. Melvin III:
Transferring Optical Proximity Correction (OPC) Effect into Optical Mode. 771-775 - Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. 776-781 - Ye Chen, Zheng Shi, Xiaolang Yan:
An Automated and Fast OPC Algorithm for OPC-Aware Layout Design. 782-787 - Yufu Zhang, Zheng Shi:
A New Method of Implementing Hierarchical OPC. 788-794
Session 6A: DFM Process
- Subarna Sinha, Qing Su, Linni Wen, Frank Lee, Charles C. Chiang, Yi-Kan Cheng, Jin-Lien Lin, Yu-Chyi Harn:
A New Flexible Algorithm for Random Yield Improvement. 795-800 - Arthur Nieuwoudt, Tamer Ragheb, Hamid Nejati, Yehia Massoud:
Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations. 801-806 - S. Ramsundar, Ahmad A. Al-Yamani, Dhiraj K. Pradhan:
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm. 807-813 - Shubhankar Basu, Priyanka Thakore, Ranga Vemuri
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. 814-820 - Kevin W. McCullen
Redundant Via Insertion in Restricted Topology Layouts. 821-828
Session 6B: PDM Physical Planning
- Chen Li, Cheng-Kok Koh:
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement. 829-834 - Hongjie Bai, Sheqin Dong, Xianlong Hong:
Congestion Driven Buffer Planning for X-Architecture. 835-840 - Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar
Probabilistic Congestion Prediction with Partial Blockages. 841-846 - Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong
OPC-Friendly Bus Driven Floorplanning. 847-852 - Hailin Jiang, Malgorzata Marek-Sadowska:
Power-Gating Aware Floorplanning. 853-860
Session 6C: Reliability and Interconnect at the System Level
- Frederic Worm, Patrick Thiran, Paolo Ienne:
Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs. 861-866 - Praveen Bhojwani, Rabi N. Mahapatra:
An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs. 867-872 - Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud:
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations. 873-878 - Ting-Chun Huang, Ümit Y. Ogras
Virtual Channels Planning for Networks-on-Chip. 879-884 - Vyas Krishnan, Srinivas Katkoori
A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits. 885-892
Session 6D: Design and Modeling for Soft Error Reliability
- Natasa Miskov-Zivanov, Diana Marculescu
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits. 893-898 - Liang Wang, Suge Yue, Yuanfu Zhao, Long Fan:
An SEU-Tolerant Programmable Frequency Divider. 899-904 - Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty:
A TMR Scheme for SEU Mitigation in Scan Flip-Flops. 905-910 - Krishnan Ramakrishnan, R. Rajaraman, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Variation Impact on SER of Combinational Circuits. 911-916 - Christian J. Hescott, Drew C. Ness, David J. Lilja:
MEMESTAR: A Simulation Framework for Reliability Evaluation over Multiple Environments. 917-922
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-27 20:15 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: