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39th ICCD 2021: Storrs, CT, USA
- 39th IEEE International Conference on Computer Design, ICCD 2021, Storrs, CT, USA, October 24-27, 2021. IEEE 2021, ISBN 978-1-6654-3219-1
- Prattay Chowdhury, Benjamin Carrión Schäfer:
Special Session: ADAPT: ANN-ControlleD System-Level Runtime Adaptable APproximate CompuTing. 1-4 - Isaías B. Felzmann
, João Fabrício Filho
Special Session: How much quality is enough quality? A case for acceptability in approximate designs. 5-8 - Di Wu, Joshua San Miguel
Special Session: When Dataflows Converge: Reconfigurable and Approximate Computing for Emerging Neural Networks. 9-12 - Arnab Raha, Soumendu Kumar Ghosh
Special Session: Approximate TinyML Systems: Full System Approximations for Extreme Energy-Efficiency in Intelligent Edge Devices. 13-16 - Lei Zhao, Youtao Zhang, Jun Yang:
Flipping Bits to Share Crossbars in ReRAM-Based DNN Accelerator. 17-24 - Zehao Chen
Block-LSM: An Ether-aware Block-ordered LSM-tree based Key-Value Storage Engine. 25-32 - Cheng Tan, Tong Geng, Chenhao Xie, Nicolas Bohm Agostini
DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications. 33-40 - Cheng-Yen Lee, Kunal Bharathi, Joellen Lansford
NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform. 41-48 - You Zhou, Ke Wang, Fei Wu, Changsheng Xie, Hao Lv:
Seer-SSD: Bridging Semantic Gap between Log-Structured File Systems and SSDs to Reduce SSD Write Amplification. 49-56 - Anuradha Chathuranga Ranasinghe, Sabih H. Gerez
Novel Ultra-Low-Voltage Flip-Flops: Near-Vth Modeling and VLSI Integration. 57-65 - Mark Connolly, Purab Ranjan Sutradhar
Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory. 66-73 - Tomoki Nakamura, Kazutaka Tomida, Shouta Kouno, Hidetsugu Irie, Shuichi Sakai:
Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation. 74-82 - Stefan Dan Ciocirlan, Dumitrel Loghin, Lavanya Ramapantulu, Nicolae Tapus
The Accuracy and Efficiency of Posit Arithmetic. 83-87 - Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. 88-92 - Justin Morris
AdaptBit-HD: Adaptive Model Bitwidth for Hyperdimensional Computing. 93-100 - Guy Eichler, Luca Piccolboni, Davide Giri, Luca P. Carloni
MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces. 101-108 - Shangshang Yao
An Efficient Hybrid Parallel Compression Approximate Multiplier. 109-116 - Ibrahim Haddadi, Issa Qiqieh, Rishad A. Shafik, Fei Xia, Mohammed A. Noaman Al-Hayanni
Run-time Configurable Approximate Multiplier using Significance-Driven Logic Compression. 117-124 - Teodor-Dumitru Ene, James E. Stine:
A Comprehensive Exploration of the Parallel Prefix Adder Tree Space. 125-129 - Jiafeng Xie, Pengzhou He, Chiou-Yng Lee:
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy. 130-137 - Raul Murillo
Energy-Efficient MAC Units for Fused Posit Arithmetic. 138-145 - Xinyu Li, Huimin Cui, Lei Liu:
NRHI: A Concurrent Non-Rehashing Hash Index for Persistent Memory. 146-153 - Zhengtao Li, Zhipeng Tan, Jianxi Chen:
HASDH: A Hotspot-Aware and Scalable Dynamic Hashing for Hybrid DRAM-NVM Memory. 154-161 - Bingzhe Li
EFM: Elastic Flash Management to Enhance Performance of Hybrid Flash Memory. 162-169 - Ben Gu, Longfei Luo
Dynamic File Cache Optimization for Hybrid SSDs with High-Density and Low-Cost Flash Memory. 170-173 - Xinxin Liu, Yu Hua, Rong Bai:
Consistent RDMA-Friendly Hashing on Remote Persistent Memory. 174-177 - Ramin Rajaei, Michael T. Niemier, Xiaobo Sharon Hu
Low-Cost Sequential Logic Circuit Design Considering Single Event Double-Node Upsets and Single Event Transients. 178-185 - Vikas Rao, Haden Ondricek, Priyank Kalla, Florian Enescu
Rectification of Integer Arithmetic Circuits using Computer Algebra Techniques. 186-195 - Guang Wang, Ziyuan Zhu, Shuan Li, Xu Cheng, Dan Meng:
Differential Testing of x86 Instruction Decoders with Instruction Operand Inferring Algorithm. 196-203 - Yohan Ko, Hwisoo So, Jinhyo Jung, Kyoungwoo Lee, Aviral Shrivastava:
Comprehensive Failure Analysis against Soft Errors from Hardware and Software Perspectives. 204-207 - Dongwei Chen
MetaTableLite: An Efficient Metadata Management Scheme for Tagged-Pointer-Based Spatial Safety. 208-211 - Kwangrae Kim, Jeonghyun Woo, Junsu Kim
HammerFilter: Robust Protection and Low Hardware Overhead Method for RowHammer. 212-219 - Suzhen Wu, Jiapeng Wu, Zhirong Shen, Zhihao Zhang
SimiEncode: A Similarity-based Encoding Scheme to Improve Performance and Lifetime of Non-Volatile Main Memory. 220-227 - Hongbin Gong, Zhirong Shen, Jiwu Shu:
Accelerating Sub-Block Erase in 3D NAND Flash Memory. 228-235 - Liang Shi, Longfei Luo
Understanding and Optimizing Hybrid SSD with High-Density and Low-Cost Flash Memory. 236-243 - Bingzhe Li
WAS-Deletion: Workload-Aware Secure Deletion Scheme for Solid-State Drives. 244-247 - Xinxin Liu, Yu Hua, Xuan Li, Qifan Liu:
Write-Optimized and Consistent RDMA-based Non-Volatile Main Memory Systems. 248-251 - Purab Ranjan Sutradhar
An Ultra-efficient Look-up Table based Programmable Processing in Memory Architecture for Data Encryption. 252-259 - Yi-Jou Hsiao, Chin-Fu Nien, Hsiang-Yun Cheng:
ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator. 260-268 - Sugil Lee, Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil
Fast and Low-Cost Mitigation of ReRAM Variability for Deep Learning Applications. 269-276 - Siqin Liu, Sushanth Karmunchi, Avinash Karanth, Soumyasanta Laha, Savas Kaya:
WiNN: Wireless Interconnect based Neural Network Accelerator. 277-284 - Jiaqi Zhang, Xiangru Chen, Sandip Ray:
Universal Neural Network Acceleration via Real-Time Loop Blocking. 285-289 - Han Zhao, Weihao Cui, Quan Chen, Jieru Zhao, Jingwen Leng, Minyi Guo:
Exploiting Intra-SM Parallelism in GPUs via Persistent and Elastic Blocks. 290-298 - Enliang Li, Subho S. Banerjee
Improved GPU Implementations of the Pair-HMM Forward Algorithm for DNA Sequence Alignment. 299-306 - Wei Zhang, Kaihua Fu, Ningxin Zheng, Quan Chen, Chao Li, Wenli Zheng, Minyi Guo:
CHARM: Collaborative Host and Accelerator Resource Management for GPU Datacenters. 307-315 - Hanyeoreum Bae, Miryeong Kwon, Donghyun Gouk, Sanghyun Han, Sungjoon Koh, Changrim Lee, Dongchul Park, Myoungsoo Jung:
Empirical Guide to Use of Persistent Memory for Large-Scale In-Memory Graph Analysis. 316-320 - Yilun Hao, Saransh Gupta, Justin Morris
Stochastic-HD: Leveraging Stochastic Computing on Hyper-Dimensional Computing. 321-325 - Hossein Golestani
HyperData: A Data Transfer Accelerator for Software Data Planes Based on Targeted Prefetching. 326-334 - Xuan Wang
UH-JLS: A Parallel Ultra-High Throughput JPEG-LS Encoding Architecture for Lossless Image Compression. 335-343 - Jeremy Giesen, Enrico Mezzetti
PRL: Standardizing Performance Monitoring Library for High-Integrity Real-Time Systems. 344-348 - Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri:
CIDAN: Computing in DRAM with Artificial Neurons. 349-356 - Ke Jia, Liang Yang, Jian Wang, Bin Lin, Hao Wang, Ruikai Shi:
Resonance-Based Power-Efficient Pulse Generator Design with Corresponding Distribution Network. 357-360 - Ziyi Chen, Ioannis Savidis:
Reconfigurable Array for Analog Applications. 361-365 - Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo:
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation. 366-373 - Marco Barbone
Efficient Table-Based Polynomial on FPGA. 374-382 - Kyunghwan Choi, Seongju Lee, Beom Woo Kang, Yongjun Park:
Legion: Tailoring Grouped Neural Execution Considering Heterogeneity on Multiple Edge Devices. 383-390 - Xiaoyang Lu
Premier: A Concurrency-Aware Pseudo-Partitioning Framework for Shared Last-Level Cache. 391-394 - Pete Ehrett, Todd M. Austin, Valeria Bertacco:
Chopin: Composing Cost-Effective Custom Chips with Algorithmic Chiplets. 395-399 - Toru Koizumi, Shu Sugita
Compiling and Optimizing Real-world Programs for STRAIGHT ISA. 400-408 - Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti, Luca Benini, Davide Rossi:
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. 409-416 - Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Tao Yang, Jingnai Feng, Xiaoyao Liang, Li Jiang:
SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network. 417-424 - Qi Pei, Seunghee Shin:
Improving the Heavy Re-encryption Overhead of Split Counter Mode Encryption for NVM. 425-432 - Yicheng Wang, Yang Liu, Peiyun Wu, Zhao Zhang:
Discreet-PARA: Rowhammer Defense with Low Cost and High Efficiency. 433-441 - Daniel Rodrigues Carvalho, André Seznec:
Conciliating Speed and Efficiency on Cache Compressors. 442-446 - Trung Le, Zhao Zhang, Zhichun Zhu:
POMI: Polling-Based Memory Interface for Hybrid Memory System. 447-455 - Xiaoming Du, Cong Li
Fault-Aware Prediction-Guided Page Offlining for Uncorrectable Memory Error Prevention. 456-463 - Yucheng Zhang, Hong Jiang, Mengtian Shi, Chunzhi Wang, Nan Jiang, Xinyun Wu:
A High-performance Post-deduplication Delta Compression Scheme for Packed Datasets. 464-471 - Yujun Liu, Bing Wei, Jigang Wu, Limin Xiao:
Erasure-Coded Multi-Block Updates Based on Hybrid Writes and Common XORs First. 472-479 - Chen Zou, Hui Zhang, Andrew A. Chien, Yang-Seok Ki:
PSACS: Highly-Parallel Shuffle Accelerator on Computational Storage. 480-487 - Ruixiang Ma
Intelligent Prediction of Flash Lifetime via Online Domain Adaptation. 488-491 - Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Model Synthesis for Communication Traces of System Designs. 492-499 - Sobhan Niknam
T-TSP: Transient-Temperature Based Safe Power Budgeting in Multi-/Many-Core Processors. 500-508 - Najmeh Nazari Bavarsad, Hosein Mohammadi Makrani, Hossein Sayadi, Lawrence Landis, Setareh Rafatirad, Houman Homayoun:
HosNa: A DPC++ Benchmark Suite for Heterogeneous Architectures. 509-516 - Kyeongrok Jo, Taewhan Kim:
Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis. 517-524 - Jinghan Zhang, Mehrshad Zandigohar, Gunar Schirner
RDP3: Rapid Domain Platform Performance Prediction for Design Space Exploration. 525-532 - Zhenbo Hu, Xiangyu Zou, Wen Xia, Yuhong Zhao, Weizhe Zhang, Donglei Wu:
Smart-DNN: Efficiently Reducing the Memory Requirements of Running Deep Neural Networks on Resource-constrained Platforms. 533-541 - Shuyu Zhang, Donglei Wu, Haoyu Jin, Xiangyu Zou, Wen Xia, Xiaojia Huang:
QD-Compressor: a Quantization-based Delta Compression Framework for Deep Neural Networks. 542-550 - Zirui Lian, Jing Cao
AGQFL: Communication-efficient Federated Learning via Automatic Gradient Quantization in Edge Heterogeneous Systems. 551-558 - Yanan Guo
ModelShield: A Generic and Portable Framework Extension for Defending Bit-Flip based Adversarial Weight Attacks. 559-562 - Lixian Ma, En Shao, Yueyuan Zhou, Guangming Tan:
WidePipe: High-Throughput Deep Learning Inference System on a Cluster of Neural Processing Units. 563-566 - Zhongming Yu, Guohao Dai, Guyue Huang, Yu Wang, Huazhong Yang:
Exploiting Online Locality and Reduction Parallelism for Sampled Dense Matrix Multiplication on GPUs. 567-574 - Jingdian Ming, Wei Cheng, Yongbin Zhou, Huizhong Li:
APT: Efficient Side-Channel Analysis Framework against Inner Product Masking Scheme. 575-582 - Zhaohui Chen, Emre Karabulut, Aydin Aysu, Yuan Ma, Jiwu Jing:
An Efficient Non-Profiled Side-Channel Attack on the CRYSTALS-Dilithium Post-Quantum Signature. 583-590 - Zi Wang, Shayan Omais Mohammed, Yiorgos Makris, Benjamin Carrión Schäfer:
Functional Locking through Omission: From HLS to Obfuscated Design. 591-598 - Yogendra Sao, Sk Subidh Ali
Security Analysis of State-of-the-art Scan Obfuscation Technique. 599-602 - Lennart M. Reimann
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. 603-607 - Khitam M. Alatoun, Shanmukha Murali Achyutha, Ranga Vemuri:
Efficient Methods for SoC Trust Validation Using Information Flow Verification. 608-616
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