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Daeyeal Lee
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2020 – today
- 2022
- [b1]Daeyeal Lee:
Logical Reasoning Techniques for VLSI Applications. University of California, San Diego, USA, 2022 - [j8]Chung-Kuan Cheng
, Chia-Tung Ho
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform. IEEE Access 10: 65971-65981 (2022) - [j7]Daeyeal Lee, Bill Lin, Chung-Kuan Cheng:
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing. ACM Trans. Archit. Code Optim. 19(1): 5:1-5:21 (2022) - [j6]Chung-Kuan Cheng
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1495-1508 (2022) - [j5]Chung-Kuan Cheng
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 30(8): 1059-1072 (2022) - 2021
- [j4]Daeyeal Lee
SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC. IEEE Embed. Syst. Lett. 13(4): 158-161 (2021) - [j3]Daeyeal Lee
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2142-2155 (2021) - [j2]Chung-Kuan Cheng
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1178-1191 (2021) - [c6]Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo:
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation. ICCD 2021: 366-373 - 2020
- [j1]Dongwon Park
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5097-5110 (2020) - [c5]Dongwon Park, Daeyeal Lee, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng:
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm. ASP-DAC 2020: 345-350 - [c4]Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park:
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT. ICCAD 2020: 158:1-158:8 - [c3]Chung-Kuan Cheng, Daeyeal Lee, Dongwon Park:
Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility. ISCAS 2020: 1-5
2010 – 2019
- 2012
- [c2]Daeyeal Lee, Ik Joon Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, ByungJun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, Ansoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun:
A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. ISSCC 2012: 430-432
2000 – 2009
- 2006
- [c1]YongJoon Kim, Myung-Hoon Yang, Youngkyu Park, Daeyeal Lee, Sungho Kang:
An Effective Test Pattern Generation for Testing Signal Integrity. ATS 2006: 279-286
Coauthor Index
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