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Lennart M. Reimann
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2020 – today
- 2024
- [i10]Lennart M. Reimann, Anschul Prashar, Chiara Ghinami, Rebecca Pelke, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. CoRR abs/2401.17819 (2024) - [i9]Lennart M. Reimann, Yadu Madhukumar Variyar, Lennet Huelser, Chiara Ghinami, Dominik Germek, Rainer Leupers:
Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction. CoRR abs/2408.04976 (2024) - 2023
- [c9]Gia Bao Thieu
, Sven Gesper
, Guillermo Payá-Vayá, Christoph Riggers
, Oliver Renke
, Till Fiedler, Jakob Marten
, Tobias Stuckenberg
, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann
, Rainer Leupers, Michael Beyer, Daniel Köhler, Alisa Jauch
, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blüthgen, Christian Sauer:
ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. DATE 2023: 1-6 - [c8]Lennart M. Reimann
, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers:
Quantitative Information Flow for Hardware: Advancing the Attack Landscape. LASCAS 2023: 1-4 - [c7]Lennart M. Reimann, Felix Staudigl, Rainer Leupers:
Automated Information Flow Analysis for Integrated Computing-in-Memory Modules. NEWCAS 2023: 1-5 - [c6]Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. VLSI-SoC 2023: 1-6 - [i8]Lennart M. Reimann, Felix Staudigl, Rainer Leupers:
Automated Information Flow Analysis for Integrated Computing-in-Memory Modules. CoRR abs/2304.05682 (2023) - [i7]Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. CoRR abs/2308.02694 (2023) - 2022
- [j2]Dominik Sisejkovic
, Farhad Merchant, Lennart M. Reimann
, Rainer Leupers:
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1716-1729 (2022) - [i6]Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers:
Quantitative Information Flow for Hardware: Advancing the Attack Landscape. CoRR abs/2211.16891 (2022) - 2021
- [j1]Dominik Sisejkovic
, Farhad Merchant, Lennart M. Reimann
, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers:
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. ACM J. Emerg. Technol. Comput. Syst. 17(3): 30:1-30:26 (2021) - [c5]Lennart M. Reimann
, Luca Hanel, Dominik Sisejkovic
, Farhad Merchant, Rainer Leupers:
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. ICCD 2021: 603-607 - [c4]Dominik Sisejkovic
, Lennart M. Reimann
, Elmira Moussavi, Farhad Merchant, Rainer Leupers:
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. VLSI-SoC 2021: 1-6 - [c3]Farhad Merchant, Dominik Sisejkovic
, Lennart M. Reimann
, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers:
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. VLSID 2021: 270-275 - [i5]Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers:
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. CoRR abs/2101.05591 (2021) - [i4]Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers:
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. CoRR abs/2107.01915 (2021) - [i3]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers:
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks. CoRR abs/2107.08695 (2021) - [i2]Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. CoRR abs/2109.02379 (2021) - 2020
- [c2]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann
, Rainer Leupers, Sascha Kegreiß:
Scaling Logic Locking Schemes to Multi-module Hardware Designs. ARCS 2020: 138-152 - [c1]Dominik Sisejkovic
, Farhad Merchant, Lennart M. Reimann
, Rainer Leupers, Massimiliano Giacometti, Sascha Kegreiß:
A secure hardware-software solution based on RISC-V, logic locking and microkernel. SCOPES 2020: 62-65 - [i1]Dominik Sisejkovic
, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers:
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. CoRR abs/2011.10389 (2020)
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