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Dong Tong 0001
Person information
- affiliation: Peking University, Microprocessor Research and Development Center, Beijing, China
Other persons with the same name
- Dong Tong 0002 — Beijing University of Technology, College of Metropolitan Transportation, China
- Dong Tong 0003 — National Fintech Evaluation Center
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2020 – today
- 2023
- [j7]Dongwei Chen
, Dong Tong
FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers. ACM Trans. Archit. Code Optim. 20(2): 30:1-30:24 (2023) - 2022
- [c28]Dongwei Chen, Dong Tong, Chun Yang, Jiangfang Yi, Xu Cheng:
FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers. PACT 2022: 532-533 - 2021
- [c27]Shuxin Zhou, Huandong Wang, Dong Tong:
Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme. ASP-DAC 2021: 216-221 - [c26]Dongwei Chen
MetaTableLite: An Efficient Metadata Management Scheme for Tagged-Pointer-Based Spatial Safety. ICCD 2021: 208-211 - 2020
- [i3]Dongwei Chen, Daliang Xu, Dong Tong, Kang Sun, Xuetao Guan, Chun Yang, Xu Cheng:
SMA: Eliminate Memory Spatial Errors via Saturation Memory Access. CoRR abs/2002.02831 (2020) - [i2]Daliang Xu, Dongwei Chen, Chun Yang, Kang Sun, Xu Cheng, Dong Tong:
DangKiller: Eliminating Dangling Pointers Efficiently via Implicit Identifier. CoRR abs/2003.00175 (2020) - [i1]Kang Sun, Daliang Xu, Dongwei Chen, Xu Cheng, Dong Tong:
S3Library: Automatically Eliminating C/C++ Buffer Overflow using Compatible Safer Libraries. CoRR abs/2004.09062 (2020)
2010 – 2019
- 2017
- [c25]Yangguo Liu, Junlin Lu, Dong Tong, Xu Cheng:
A Staged Memory Resource Management Method for CMP systems. ASAP 2017: 91-98 - [c24]Yangguo Liu, Junlin Lu, Dong Tong, Xu Cheng:
Locality-aware bank partitioning for shared DRAM MPSoCs. ASP-DAC 2017: 770-775 - 2016
- [c23]Yan Sui, Chun Yang, Dong Tong, Xianhua Liu
MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications. ICCD 2016: 576-583 - 2014
- [j6]Zichao Xie, Dong Tong, Mingkai Huang:
A General Low-Cost Indirect Branch Prediction Using Target Address Pointers. J. Comput. Sci. Technol. 29(6): 929-946 (2014) - [c22]Mingli Xie, Dong Tong, Kan Huang, Xu Cheng:
Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning. HPCA 2014: 344-355 - 2013
- [c21]Xianglei Dang, Xiaoyin Wang, Dong Tong, Zichao Xie, Lingda Li, Keyi Wang:
An adaptive filtering mechanism for energy efficient data prefetching. ASP-DAC 2013: 332-337 - [c20]Qiaoli Xiong, Jiangfang Yi, Tianbao Song, Zichao Xie, Dong Tong:
VFCC: A verification framework of cache coherence using parallel simulation. ASP-DAC 2013: 705-710 - [c19]Zichao Xie, Dong Tong, Xu Cheng:
An energy-efficient branch prediction technique via global-history noise reduction. ISLPED 2013: 211-216 - [c18]Mingli Xie, Dong Tong, Yi Feng, Kan Huang, Xu Cheng:
Page policy control with memory partitioning for DRAM performance and power efficiency. ISLPED 2013: 298-303 - [c17]Ning Jia
SPIRE: improving dynamic binary translation through SPC-indexed indirect branch redirecting. VEE 2013: 1-12 - 2012
- [j5]Zichao Xie, Dong Tong, Mingkai Huang, Qinqing Shi, Xu Cheng:
SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers. J. Comput. Sci. Technol. 27(4): 754-768 (2012) - [j4]Zhen-Hao Zhang, Xiaoyin Wang, Dong Tong, Jiangfang Yi, Junlin Lu, Keyi Wang:
Active Store Window: Enabling Far Store-Load Forwarding with Scalability and Complexity-Efficiency. J. Comput. Sci. Technol. 27(4): 769-780 (2012) - [c16]Lingda Li
Optimal bypass monitor for high performance last-level caches. PACT 2012: 315-324 - [c15]Mingxing Tan, Xianhua Liu, Zichao Xie, Dong Tong, Xu Cheng:
Energy-efficient branch prediction with Compiler-guided History Stack. DATE 2012: 449-454 - [c14]Xianglei Dang, Xiaoyin Wang, Dong Tong, Junlin Lu, Jiangfang Yi, Keyi Wang:
S/DC: A storage and energy efficient data prefetcher. DATE 2012: 461-466 - [c13]Zhen-Hao Zhang, Dong Tong, Xiaoyin Wang, Jiangfang Yi, Keyi Wang:
SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency. ICCD 2012: 291-296 - [c12]Lingda Li, Dong Tong, Zichao Xie, Junlin Lu, Xu Cheng:
Improving inclusive cache performance with two-level eviction priority. ICCD 2012: 387-392 - 2011
- [c11]Zichao Xie, Dong Tong, Mingkai Huang, Xiaoyin Wang, Qinqing Shi, Xu Cheng:
TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers. ICCD 2011: 119-126 - [c10]Liucheng Guo, Jiangfang Yi, Liang Zhang, Xiaoyin Wang, Dong Tong:
CGA: Combining cluster analysis with genetic algorithm for regression suite reduction of microprocessors. SoCC 2011: 207-212 - 2010
- [j3]Xu Cheng, Xiaoyin Wang, Junlin Lu, Jiangfang Yi, Dong Tong, Xuetao Guan, Feng Liu, Xianhua Liu, Chun Yang, Yi Feng:
Research Progress of UniCore CPUs and PKUnity SoCs. J. Comput. Sci. Technol. 25(2): 200-213 (2010) - [c9]Hao Li, Dong Tong, Kan Huang, Xu Cheng:
FEMU: a firmware-based emulation framework for SoC verification. CODES+ISSS 2010: 257-266 - [c8]Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong, Xu Cheng:
FPGA prototyping of an amba-based windows-compatible SoC. FPGA 2010: 13-22 - [c7]Shu Liu, Xu Cheng, Xuetao Guan, Dong Tong:
Energy efficient management scheme for heterogeneous secondary storage system in mobile computers. SAC 2010: 251-257 - [c6]Dan Liu, Yi Feng, Jingjin Zhou, Dong Tong, Xu Cheng, Keyi Wang:
TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures. SoCC 2010: 182-187
2000 – 2009
- 2009
- [c5]Yansong Zheng, Dong Tong, Hao Li, Keyi Wang, Xu Cheng:
Track Down HW Function Faults Using Real SW Invariants. CSIE (3) 2009: 248-253 - [c4]Zichao Xie, Dong Tong, Xu Cheng:
WHOLE: A low energy I-Cache with separate way history. ICCD 2009: 137-143 - 2008
- [j2]Han-Xin Sun, Kun-Peng Yang, Yulai Zhao, Dong Tong, Xu Cheng:
CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs. J. Comput. Sci. Technol. 23(1): 141-153 (2008) - 2007
- [j1]Yulai Zhao, Xianfeng Li, Dong Tong, Xu Cheng:
An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking. J. Comput. Sci. Technol. 22(1): 15-24 (2007) - [c3]Yi Feng, Zheng Zhou, Dong Tong, Xu Cheng:
Clock domain crossing fault model and coverage metric for validation of SoC design. DATE 2007: 1385-1390 - [c2]Yulai Zhao, Xianfeng Li, Dong Tong, Xu Cheng:
Reuse Distance Based Cache Leakage Control. HiPC 2007: 356-367 - 2005
- [c1]Qiang Liu, Dong Tong, Xu Cheng:
Non-interleaving architecture for hardware implementation of modular multiplication. ISCAS (1) 2005: 660-663
Coauthor Index
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