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16. ACM Great Lakes Symposium on VLSI 2006: Philadelphia, PA, USA
- Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou:
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006. ACM 2006, ISBN 1-59593-347-6 - Dan Page, Jamil Kawa, Charles C. Chiang:
DFM: swimming upstream. 1
Emerging technologies
- Garrett S. Rose
, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan
Design approaches for hybrid CMOS/molecular memory based on experimental device data. 2-7 - Rui Zhang, Niraj K. Jha:
Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations. 8-13 - Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal:
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies. 14-18 - Kiran Puttaswamy, Gabriel H. Loh:
Thermal analysis of a 3D die-stacked high-performance microprocessor. 19-24
CAD for embedded systems
- Young-Jun Kim, Taewhan Kim:
HW/SW partitioning techniques for multi-mode multi-task embedded applications. 25-30 - Franco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino:
ISS-centric modular HW/SW co-simulation. 31-36 - Ozcan Ozturk, Mahmut T. Kandemir, Suleyman Tosun:
An ILP based approach to address code generation for digital signal processors. 37-42 - Daniel Große, Ulrich Kühne, Rolf Drechsler:
HW/SW co-verification of embedded systems using bounded model checking. 43-48
RF and data communication circuits
- Rui Tang, Yong-Bin Kim:
PWAM signalling scheme for high speed serial link transceiver design. 49-52 - Hung Tien Bui, Yvon Savaria:
High speed differential pulse-width control loop based on frequency-to-voltage converters. 53-56 - Abhishek Jajoo, Michael Sperling, Tamal Mukherjee
Synthesis of a wideband low noise amplifier. 57-62 - Minghai Li, Fei Yuan:
A 0.13µm CMOS 10 Gb/s current-mode class AB serial link transmitter with low supply voltage sensitivity. 63-66
Partitioning and floorplanning
- David Bañeres, Jordi Cortadella
Dominator-based partitioning for delay optimization. 67-72 - Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani:
How does partitioning matter for 3D floorplanning? 73-78 - Chang Woo Kang, Massoud Pedram:
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs. 79-84 - Royce L. S. Ching, Evangeline F. Y. Young:
Shuttle mask floorplanning with modified alpha-restricted grid. 85-90
Poster session 1
- Xiangyuan Liu, Shuming Chen:
Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning. 91-94 - Ayse K. Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli:
A simulation methodology for reliability analysis in multi-core SoCs. 95-99 - Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail:
Power density minimization for highly-associative caches in embedded processors. 100-104 - Lara D. Oliver, Krishnendu Chakrabarty
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques. 105-110 - Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra:
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction. 111-114 - Zuying Luo:
General transistor-level methodology on VLSI low-power design. 115-118 - K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
Delay and peak power minimization for on-chip buses using temporal redundancy. 119-122 - Zhiyuan Li, Fengchang Lai, Mingyan Yu:
Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology. 123-126 - Fei Yuan:
A new power-area efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10Gb/s serial links. 127-130 - Jun-Da Chen, Zhi-Ming Lin:
A low-power and high-linear double-balanced switching mixer. 131-134 - Yarallah Koolivand, Omid Shoaei, Ali Fotowat-Ahmady, Ali Zahabi, Parviz Jabedar Maralani:
Nonlinearity Analysis in ISD CMOS LNA's Using Volterra Series. 135-139 - Qianneng Zhou, Fengchang Lai, Mingyan Yu:
On-chip 3.3V-to-1.8V voltage down converter for low-power VLSI chips. 140-143 - Hung D. Nguyen, Benjamin J. Blalock, Suheng Chen:
A SiGe BiCMOS linear regulator with wideband, high power supply rejection. 144-148 - Kundan Nepal, R. Iris Bahar
Optimizing noise-immune nanoscale circuits using principles of Markov random fields. 149-152 - Kiran Puttaswamy, Gabriel H. Loh:
Dynamic instruction schedulers in a 3-dimensional integration technology. 153-158 - Song Peng, Rajit Manohar:
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. 159-164 - William R. Roberts, Dimitrios Velenis:
Effects of process and environmental variations on timing characteristics of clocked registers. 165-168 - Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya:
On finding the minimum test set of a BDD-based circuit. 169-172
Circuit design and modeling
- Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu:
Maximum effective distance of on-chip decoupling capacitors in power distribution grids. 173-179 - Bo Shen, Sunil P. Khatri, Takis Zourntos:
Implementation of MOSFET based capacitors for digital applications. 180-186 - Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud:
Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration. 187-191
High performance VLSI design
- Jonathan Rosenfeld, Eby G. Friedman:
Sensitivity evaluation of global resonant H-tree clock distribution networks. 192-197 - Rashed Zafar Bhatti, Monty Denneau, Jeff Draper:
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. 198-203 - Sergio Tota, Mario R. Casu, Luca Macchiarulo:
Implementation analysis of NoC: a MPSoC trace-driven approach. 204-209 - Jeff Parkhurst:
From single core to multi-core to many core: are we ready for a new exponential? 210
Timing optimization
- Hosung (Leo) Kim, John Lillis, Milos Hrkic:
Techniques for improved placement-coupled logic replication. 211-216 - Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri:
A design flow to optimize circuit delay by using standard cells and PLAs. 217-222 - Andrew B. Kahng, Bao Liu, Xu Xu:
Statistical gate delay calculation with crosstalk alignment consideration. 223-228 - Joonsoo Kim, Michael Orshansky:
Towards formal probabilistic power-performance design space exploration. 229-234
Testing and noise analysis
- Chuen-Song Chen, Jien-Chung Lo, Tian Xia:
An indirect current sensing technique for IDDQ and IDDT tests. 235-240 - Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer:
SACI: statistical static timing analysis of coupled interconnects. 241-246 - Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich:
Performance verification of high-performance ASICs using at-speed structural test. 247-252 - Shahin Nazarian, Ali Iranli, Massoud Pedram:
Crosstalk analysis in nanometer technologies. 253-258
System and architectural-Level VLSI design
- Talal Bonny
Using Lin-Kernighan algorithm for look-up table compression to improve code density. 259-265 - Hima B. Damecharla, Kamal K. Varma, Joan Carletta, Amy E. Bell:
FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiency. 266-271 - Xinmiao Zhang:
Partial parallel factorization in soft-decision Reed-Solomon decoding. 272-277
Low power design and technology
- Ali Bastani, Charles A. Zukowski:
Monotonic static CMOS tradeoffs in sub-100nm technologies. 278-283 - Vahid Majidzadeh, Omid Shoaei:
A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs. 284-289 - Wei-Chung Cheng, Chain-Fu Chao:
Perception-guided power minimization for color sequential displays. 290-295
Poster session 2
- Zhonghai Lu, Mingchen Zhong, Axel Jantsch:
Evaluation of on-chip networks using deflection routing. 296-301 - Lun Li, Mitchell A. Thornton, David W. Matula:
A digit serial algorithm for the integer power operation. 302-307 - Scott J. Campbell, Sunil P. Khatri:
Resource and delay efficient matrix multiplication using newer FPGA devices. 308-311 - Yongmei Dai, Zhiyuan Yan, Ning Chen:
Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes. 312-315 - Bo Fu, Qiaoyan Yu, Paul Ampadu:
Energy-delay minimization in nanoscale domino logic. 316-319 - Luciano Volcan Agostini
High throughput architecture for H.264/AVC forward transforms block. 320-323 - Sathish Chandra, Francesco Regazzoni, Marcello Lajolo:
Hardware/software partitioning of operating systems: a behavioral synthesis approach. 324-329 - Mohamed H. Zaki, Sofiène Tahar, Guy Bois:
A practical approach for monitoring analog circuits. 330-335 - Xu Zhang, Xiaohong Jiang, Susumu Horiguchi:
A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effects. 336-340 - Jinwen Xi, Peixin Zhong:
A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models. 341-344 - Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
A formal approach for high level synthesis of linear analog systems. 345-348 - Renqiu Huang, Ranga Vemuri
Transformation synthesis for data intensive applications to FPGAs. 349-352 - Mohamed El-Nozahi, Yehia Massoud:
An integrated circuit/behavioral simulation framework for continuous-time sigma-delta ADCs. 353-356 - Marios Kalathas, Dimitrios Voudouris, George K. Papakonstantinou:
A heuristic algorithm to minimize ESOPs for multiple-output incompletely specified functions. 357-361 - Heon-Mo Koo, Prabhat Mishra
Test generation using SAT-based bounded model checking for validation of pipelined processors. 362-365 - I-Lun Tseng, Adam Postula:
An efficient algorithm for partitioning parameterized polygons into rectangles. 366-371 - Murari Mani, Mahesh Sharma, Michael Orshansky:
Application of fast SOCP based statistical sizing in the microprocessor design flow. 372-375 - Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching:
Block alignment in 3D floorplan using layered TCG. 376-380 - Paul P. Sotiriadis
Rapid intermodulation distortion estimation in fully balanced weakly nonlinear Gm-C filters using state-space modeling. 381-385
System & architectural-level power optimization
- Ozcan Ozturk, Mahmut T. Kandemir, Seung Woo Son, Mustafa Karaköy:
Selective code/data migration for reducing communication energy in embedded MpSoC architectures. 386-391 - Changjiu Xian, Yung-Hsiang Lu:
Dynamic voltage scaling for multitasking real-time systems with uncertain execution time. 392-397 - Xiangrong Zhou, Peter Petrov:
Low-power cache organization through selective tag translation for embedded processors with virtual memory support. 398-403 - Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino:
STV-Cache: a leakage energy-efficient architecture for data caches. 404-409
Power aware digital circuits
- Ranjith Kumar, Volkan Kursun
A design methodology for temperature variation insensitive low power circuits. 410-415 - Giby Samson
Circuit architecture for low-power race-free programmable logic arrays. 416-421 - Qingli Zhang, Jinxiang Wang, Yizheng Ye:
An energy-efficient temporal encoding circuit technique for on-chip high performance buses. 422-427 - Zhiyu Liu, Volkan Kursun
Leakage current starved domino logic. 428-433
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