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Kundan Nepal
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2020 – today
- 2024
- [c27]Alexander Coyle, Hui Jiang, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal:
Dual Use Circuitry for Early Failure Warning and Test. ISQED 2024: 1-8 - 2023
- [j14]Hui Jiang
, Fanchen Zhang, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift. J. Electron. Test. 39(2): 227-243 (2023) - [c26]Eslam Yassien, Yongjia Xu, Hui Jiang, Thach Nguyen, Jennifer Dworak, Theodore W. Manikas
Harvesting Wasted Clock Cycles for Efficient Online Testing. ETS 2023: 1-6 - 2022
- [j13]Dulana Rupanetti, Hassan A. Salamy, Cheol-Hong Min, Kundan Nepal:
Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis. Int. J. Parallel Emergent Distributed Syst. 37(6): 696-713 (2022) - 2021
- [j12]Soha Alhelaly
3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations. IEEE Trans. Emerg. Top. Comput. 9(2): 774-786 (2021) - [c25]Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. ITC 2021: 319-323 - 2020
- [c24]Dulana Rupanetti, Kundan Nepal, Hassan A. Salamy, Cheol-Hong Min:
Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications. CCWC 2020: 228-233
2010 – 2019
- 2019
- [j11]Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. J. Electron. Test. 35(6): 887-900 (2019) - [j10]Daniel Hellkamp, Kundan Nepal:
True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors. J. Circuits Syst. Comput. 28(5): 1950085:1-1950085:18 (2019) - [c23]Milad Audi, William Frost, Jose Henriquez, Nathan Jones, Janssen Hang, Kundan Nepal:
Low cost Brussels sprouts harvester for small farms. GHTC 2019: 1-4 - [c22]Jeremy Ziemer, Austin Stokes, Janssen Hang, Kundan Nepal:
Low-cost instrumentation of high-tunnels for a small co-op farm. GHTC 2019: 1-4 - [c21]Matthew Ward, Cheol-Hong Min, Hassan A. Salamy, Kundan Nepal:
Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition. ICECS 2019: 49-52 - [c20]Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas
Test Architecture for Fine Grained Capture Power Reduction. ICECS 2019: 558-561 - 2018
- [c19]Heath J. LeBlanc, Kundan Nepal, Greg S. Mowry, Alan Cheville:
Tools for the 3Cs of Entrepreneurially Minded Learning (EML). FIE 2018: 1-3 - 2017
- [c18]Heath J. LeBlanc, Kundan Nepal, Greg S. Mowry:
Stimulating curiosity and the ability to formulate technical questions in an electric circuits course using the question formulation technique (QFT). FIE 2017: 1-6 - [c17]Noah Cornell, Kundan Nepal:
Combinational hardware Trojan detection using logic implications. MWSCAS 2017: 571-574 - [c16]Soha Alhelaly, Jennifer Dworak, Theodore W. Manikas
Detecting a trojan die in 3D stacked integrated circuits. NATW 2017: 1-6 - 2016
- [c15]Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas
Using Existing Reconfigurable Logic in 3D Die Stacks for Test. NATW 2016: 46-52 - 2015
- [j9]Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar
Repairing a 3-D Die-Stack Using Available Programmable Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 849-861 (2015) - 2013
- [c14]Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas
Built-in Self-Repair in a 3D die stack using programmable logic. DFTS 2013: 243-248 - 2012
- [j8]Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar
Using implications to choose tests through suspect fault identification. ACM Trans. Design Autom. Electr. Syst. 18(1): 14:1-14:19 (2012) - [c13]Kundan Nepal:
Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors. NEWCAS 2012: 421-424 - 2011
- [j7]Carson Dunbar, Kundan Nepal:
Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults. J. Comput. 6(11): 2335-2344 (2011) - [c12]Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. ETS 2011: 211 - [c11]Maurice F. Aburdene, Kundan Nepal:
Wow! linear systems and signal processing is fun! FIE 2011: 1 - [c10]Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar
Enhancing online error detection through area-efficient multi-site implications. VTS 2011: 241-246 - 2010
- [j6]Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
A Cost Effective Approach for Online Error Detection Using Invariant Relationships. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 788-801 (2010) - [c9]Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
Improving the testability and reliability of sequential circuits with invariant logic. ACM Great Lakes Symposium on VLSI 2010: 131-134
2000 – 2009
- 2009
- [c8]Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
Detecting errors using multi-cycle invariance information. DATE 2009: 791-796 - [c7]Nuno Alves, Jennifer Dworak, R. Iris Bahar
Compacting test vector sets via strategic use of implications. ICCAD 2009: 83-88 - 2008
- [c6]Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar
Using Implications for Online Error Detection. ITC 2008: 1-10 - 2007
- [j5]Kundan Nepal, R. Iris Bahar
Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electron. Test. 23(2-3): 255-266 (2007) - [c5]Kundan Nepal, R. Iris Bahar
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE 2007: 576-581 - 2006
- [j4]Kundan Nepal, R. Iris Bahar
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. IEEE Micro 26(5): 19-27 (2006) - [j3]Hui-Yuan Song, Kundan Nepal, R. Iris Bahar
Timing analysis for full-custom circuits using symbolic DC formulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1815-1830 (2006) - [c4]Kundan Nepal, R. Iris Bahar
Designing MRF based error correcting circuits for memory elements. DATE 2006: 792-793 - [c3]Kundan Nepal, R. Iris Bahar
Optimizing noise-immune nanoscale circuits using principles of Markov random fields. ACM Great Lakes Symposium on VLSI 2006: 149-152 - 2005
- [j2]R. Iris Bahar
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 502-515 (2005) - [c2]Kundan Nepal, R. Iris Bahar
Designing logic circuits for probabilistic computation in the presence of noise. DAC 2005: 485-490 - 2004
- [j1]Michelle Bovard, Matthew Gillette, Trishan R. de Lanerolle, Bozidar Marinkovic, Nhon H. Trinh, Peter Votto, David J. Ahlgren, Kundan Nepal, Amir Tamrakar:
Design evolution of the Trinity College IGVC robot ALVIN. J. Field Robotics 21(9): 461-469 (2004) - [c1]Kundan Nepal, Hui-Yuan Song, R. Iris Bahar
RESTA: a robust and extendable symbolic timing analysis tool. ACM Great Lakes Symposium on VLSI 2004: 407-412
Coauthor Index
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last updated on 2024-06-06 22:11 CEST by the dblp team
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