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Ivan Saraiva Silva
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2020 – today
- 2023
- [c36]Ivan Saraiva Silva, Francisco Carlos Silva Junior:
X4-RARE: Revisiting the X4CP32 Coarse-Grained Reconfigurable Architecture Model. ISVLSI 2023: 1-6 - 2022
- [c35]Valeria Barzola, Eddo Alvarado, Carlos Loja, Alex Velez, Ivan Saraiva Silva, Vanessa Echeverría
:
Analyzing Speech Data to Detect Work Environment in Group Activities. AIED (2) 2022: 357-361 - [c34]Lucas Ribeiro, Ricardo P. Jacobi, Francisco Júnior, Jones Yudi Mori Alves da Silva, Ivan Saraiva Silva:
Evaluating a Machine Learning-based Approach for Cache Configuration. LASCAS 2022: 1-4 - 2021
- [c33]Francisco Carlos Silva, Ivan Saraiva Silva:
A Redundant Approach to Increase Reliability of Data Cache Memories. CLEI 2021: 1-7 - 2020
- [c32]Francisco Carlos Silva, João P. dos S. Patrocinio, Ivan Saraiva Silva, Ricardo Pezzuol Jacobi
Design Space Exploration of a Reconfigurable Accelerator in a Heterogeneous Multicore. SBCCI 2020: 1-6
2010 – 2019
- 2019
- [c31]José Carlos C. L. da Silva Filho, Fábbio Anderson Silva Borges, Ricardo de Andrade Lira Rabelo, Ivan Saraiva Silva:
A Method for Voltage Sag Source Location Using Clustering Algorithm and Decision Rule Labeling. IJCNN 2019: 1-8 - 2016
- [c30]Francisco Carlos Silva Junior, Ivan Saraiva Silva:
Proposal and validation of an adaptable array for multi-core processors. CLEI 2016: 1-7 - [c29]Joselito Mendes de Sousa, Roney Lira de Sales Santos
Automatic labelling of clusters with discrete and continuous data using supervised machine learning. SCCC 2016: 1-10 - 2015
- [c28]Ivan Saraiva Silva, Hildebrando Segundo:
Scratchpad memory management using data-prefetching. CLEI 2015: 1-7 - [c27]Thiago R. B. S. Soares, Ivan Saraiva Silva, Sílvio R. F. de Fernandes:
IPNoSys II: A New Architecture for IPNoSys Programming Model. SBCCI 2015: 40:1-40:7 - [c26]Ramon S. Nepomuceno, Jonatas C. Santos, Laysson O. Luz, Ivan Saraiva Silva:
An OpenCL-Compliant Multi-core Platform and Its Companion Compiler. SBESC 2015: 116-121 - 2012
- [j5]Sílvio R. F. de Araújo, Ivan Saraiva Silva:
Operating System Support for IPNoSys. CLEI Electron. J. 15(2) (2012) - [j4]Alba Sandyra Bezerra Lopes
A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos. Int. J. Reconfigurable Comput. 2012: 473725:1-473725:10 (2012) - [c25]Ivan Saraiva Silva, Ramon Nepomuceno, Tackyss Mafuta, Eeugenio S. Carvalho:
uVMP: Virtualizable multi-core platform. CLEI 2012: 1-6 - [c24]Leonardo Augusto Casillo, Ivan Saraiva Silva:
A Methodology to Adapt Data Path Architectures to a MIPS-1 Model. SBESC 2012: 172-177 - 2011
- [c23]Ivan Saraiva Silva, Sílvio R. F. de Fernandes, Leonardo Augusto Casillo:
ZONA - An adaptable NoC-based multiprocessor addressed to education on system-on-chip design. MSE 2011: 108-111 - [c22]Alba Sandyra Bezerra Lopes
An efficient memory hierarchy for full search motion estimation on high definition digital videos. SBCCI 2011: 131-136 - [c21]Hadley M. Siqueira, Ivan Saraiva Silva, Márcio Eduardo Kreutz, Edgard de Faria Corrêa:
DDR SDRAM Memory Controller for Digital TV Decoders. SBESC 2011: 78-82 - 2010
- [c20]Bruno Cruz de Oliveira, Márcio Eduardo Kreutz, Edgard de Faria Corrêa, Ivan Saraiva Silva:
Exploring memory organization in virtual MP-SoC platforms. SBCCI 2010: 79-84
2000 – 2009
- 2009
- [j3]Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, M. Costa, Ivan Saraiva Silva:
Processing while routing: a network-on-chipbased parallel system. IET Comput. Digit. Tech. 3(5): 525-538 (2009) - [c19]Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, Ivan Saraiva Silva:
Using NoC routers as processing elements. SBCCI 2009 - [e1]Ivan Saraiva Silva, Renato P. Ribas, Calvin Plett:
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009. ACM 2009, ISBN 978-1-60558-705-9 [contents] - 2008
- [c18]Monica Magalhães Pereira, Sílvio R. F. de Araújo, Bruno Cruz de Oliveira, Ivan Saraiva Silva:
Using traditional loop unrolling to fit application on a new hybrid reconfigurable architecture. SAC 2008: 1552-1553 - 2007
- [j2]Luciano Volcan Agostini
Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs. Microprocess. Microsystems 31(8): 487-497 (2007) - [c17]Monica Magalhães Pereira, Bruno Cruz de Oliveira, Ivan Saraiva Silva:
RoSA: a reconfigurable stream-based architecture. SBCCI 2007: 159-164 - [c16]Gustavo Girão, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva:
Cache coherency communication cost in a NoC-based MPSoC platform. SBCCI 2007: 288-293 - 2006
- [c15]Luciano Volcan Agostini
High throughput architecture for H.264/AVC forward transforms block. ACM Great Lakes Symposium on VLSI 2006: 320-323 - [c14]Luciano Volcan Agostini
High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAs. ICECS 2006: 180-183 - [c13]Luciano Volcan Agostini
High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard. ISCAS 2006 - [c12]Gustavo Girão, Sílvio R. F. de Araújo, Monica Magalhães Pereira, Ivan Saraiva Silva:
Implementation of a HDTV transport stream multiplexer based on ITU-T H.222.0 recommendation. WebMedia 2006: 1-9 - 2005
- [c11]Luciano Volcan Agostini
A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor. DSD 2005: 210-213 - 2004
- [j1]Luciano Volcan Agostini
Parallel color space converters for JPEG image compression. Microelectron. Reliab. 44(4): 697-703 (2004) - [c10]Frederiko Stenio de Araújo, Karla Darlene Nempomuceno Ramos, Benjamín René Callejas Bedregal, Ivan Saraiva Silva:
Papílio Cryptography Algorithm. CIS 2004: 928-933 - [c9]Marcos R. Boschetti, Ivan Saraiva Silva, Sergio Bampi
A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications. DATE 2004: 242-247 - [c8]Marcos R. Boschetti, Sergio Bampi
Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters. FPL 2004: 474-483 - [c7]Rodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo:
When reconfigurable architecture meets network-on-chip. SBCCI 2004: 216-221 - 2003
- [c6]Rodrigo Soares, Arnaldo Azevedo, Ivan Saraiva Silva:
X4CP32: A Coarse Grain General Purpose Reconfigurable Microprocessor. IPDPS 2003: 171 - [c5]Rodrigo Soares, Arnaldo Azevedo, Ivan Saraiva Silva:
X4CP32: A New Parallel/Reconfigurable General-Purpose Processor. SBAC-PAD 2003: 260-268 - [c4]Arnaldo Azevedo, Rodrigo Soares, Ivan Saraiva Silva:
A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32. SBCCI 2003: 225-230 - 2002
- [c3]Marcos R. Boschetti, Alexandro M. S. Adário, Ivan Saraiva Silva, Sergio Bampi:
Techniques and Mechanisms for Dynamic Reconfiguration in an Image Processor. SBCCI 2002: 177-182 - [c2]Luciano Volcan Agostini, Ivan Saraiva Silva, Sergio Bampi:
Pipelined Entropy Coders for JPEG Compression. SBCCI 2002: 203-208 - 2001
- [c1]Luciano Volcan Agostini, Sergio Bampi, Ivan Saraiva Silva:
Pipelined Fast 2-D DCT Architecture for JPEG Image Compression. SBCCI 2001: 226-231
Coauthor Index
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