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19. FPGA 2011: Monterey, CA, USA
- John Wawrzynek, Katherine Compton:
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011. ACM 2011, ISBN 978-1-4503-0554-9
Workshop
- Jonathan Rose, Guy G. Lemieux:
The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. 1-2
Panel
- John Wawrzynek:
Should the academic community launch an open-source FPGA device and tools effort?: evening panel. 3-4
FPGA-based computing systems
- Henry Wong, Vaughn Betz, Jonathan Rose:
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. 5-14 - Christopher Han-Yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy G. Lemieux:
VEGAS: soft vector processor with scratchpad memory. 15-24 - Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer:
Leap scratchpads: automatic memory and cache management for reconfigurable logic. 25-28 - Martin Labrecque, J. Gregory Steffan:
NetTM: faster and easier synchronization for soft multicores via transactional memory. 29-32 - Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski:
LegUp: high-level synthesis for FPGA-based processor/accelerator systems. 33-36 - Ling Liu, Oleksii Morozov, Yuxing Han, Jürg Gutknecht, Patrick R. Hunziker:
Automatic SoC design flow on many-core processors: a software hardware co-design approach for FPGAs. 37-40 - Neil Steiner, Aaron Wood, Hamid Shojaei, Jacob Couch
, Peter Athanas, Matthew French:
Torc: towards an open-source tool flow. 41-44
Applications I
- Dirk Koch, Jim Tørresen:
FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting. 45-54 - Lu Zhang, Ke Zhang, Tian Sheuan Chang
Real-time high-definition stereo matching on FPGA. 55-64 - Haohuan Fu, Robert G. Clapp:
Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration. 65-74 - Tim Papenfuss, Holger Michel:
A platform for high level synthesis of memory-intensive image processing algorithms. 75-78 - Qiang Gao, Robert W. Stewart:
Improved double angle complex rotation QRD-RLS. 79-82 - Steven Trimberger, Jason Moore, Weiguang Lu:
Authenticated encryption for FPGA bitstreams. 83-86
FPGA architectures and technology
- Jonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner:
A 65nm flash-based FPGA fabric optimized for low cost and power. 87-96 - Eric S. Chung, James C. Hoe, Ken Mai
CoRAM: an in-fabric memory architecture for FPGA-based computing. 97-106 - Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck:
Energy-efficient specialization of functional units in a coarse-grained reconfigurable array. 107-110 - Abdullah Nazma Nowroz, Sherief Reda:
Thermal and power characterization of field-programmable gate arrays. 111-114 - Juergen Ributzka, Yuhei Hayashi, Fei Chen, Guang R. Gao:
DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research. 115-118 - Christopher W. Fletcher, Ilia A. Lebedev, Narges Bani Asadi, Daniel Burke, John Wawrzynek:
Bridging the GPGPU-FPGA efficiency gap. 119-122
CAD
- David Grant, Chris C. Wang, Guy G. Lemieux:
A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements. 123-132 - Doris Chen, Deshanand P. Singh
Line-level incremental resynthesis techniques for FPGAs. 133-142 - Scott Y. L. Chin, Steven J. E. Wilton:
Towards scalable FPGA CAD through architecture. 143-152
CAD, measurement, and estimation
- Chris C. Wang, Guy G. Lemieux:
Scalable and deterministic timing-driven parallel placement for FPGAs. 153-162 - Justin S. J. Wong
Improved delay measurement method in FPGA based on transition probability. 163-172 - Raphael Rubin, André DeHon:
Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder. 173-176 - Tobias Kenter, Christian Plessl
Performance estimation framework for automated exploration of CPU-accelerator architectures. 177-180 - Joydip Das, Steven J. E. Wilton:
An analytical model relating FPGA architecture parameters to routability. 181-184 - Satnam Singh:
The RLOC is dead - long live the RLOC. 185-188
Applications II
- Charles Lo, Paul Chow:
Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI. 189-198 - Jackson H. C. Yeung, Evangeline F. Y. Young, Philip Heng Wai Leong
A monte-carlo floating-point unit for self-validating arithmetic. 199-208 - Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan:
An FPGA implementation of a sparse quadratic programming solver for constrained predictive control. 209-218 - Abhay Tavaragiri, Jacob Couch
Exploration of FPGA interconnect for the design of unconventional antennas. 219-226
FPGA CAD and architecture
- Jason Luu, Jason Helge Anderson, Jonathan Rose:
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. 227-236 - Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk
Reducing the pressure on routing resources of FPGAs with generic logic chains. 237-246 - Andrei Hagiescu, Weng-Fai Wong
Co-synthesis of FPGA-based application-specific floating point simd accelerators. 247-256
Networking and security
- Hoang Le, Thilan Ganegedara, Viktor K. Prasanna:
Memory-efficient and scalable virtual routers using FPGA. 257-266 - Ji Sun, Ray Bittner, Ken Eguro:
FPGA side-channel receivers. 267-276
Poster session 1
- Alfio Lombardo, Diego Reforgiato Recupero, Giovanni Schembra:
An accelerated and energy-efficient traffic monitor using the NetFPGA (abstract only). 277 - Daniel Schinke, Wallace Shep Pitts, Neil Di Spigna, Paul D. Franzon:
Low power interconnect design for fpgas with bidirectional wiring using nanocrystal floating gate devices (abstract only). 277 - Steve Richfield:
Dealing with the "itanium effect" (abstract only). 277 - Haile Yu, Qiang Xu, Philip Heng Wai Leong:
On timing yield improvement for FPGA designs using architectural symmetry (abstract only). 278 - Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis:
High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only). 278 - Jason Cong, Yi Zou:
Resolving implicit barrier synchronizations in FPGA HLS (abstract only). 278 - Peter Grossmann, Miriam Leeser:
A prototype FPGA for subthreshold-optimized CMOS (abstract only). 279 - Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He:
Fault modeling and characteristics of SRAM-based FPGAs (abstract only). 279
Poster session 2
- Srinidhi Kestur, Dharav Dantara, Vijaykrishnan Narayanan:
A streaming FPGA implementation of a steerable filter for real-time applications (abstract only). 281 - Mingjie Lin, Shaoyi Cheng, John Wawrzynek:
Using many-core architectural templates for FPGA-based computing (abstract only). 281 - Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan:
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). 281 - Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk:
A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only). 281 - Hock Soon Low, Delong Shang, Fei Xia, Alexandre Yakovlev:
Variation tolerant asynchronous FPGA (abstract only). 282
Poster session 3
- Fadi Obeidat, Robert H. Klenke:
Microblaze: an application-independent fpga-based profiler (abstract only). 283 - Andrew W. Hill
FPGA-based fine-grain parallel computing (abstract only). 283 - Somnath Paul, Swarup Bhunia:
Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only). 283 - Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). 284 - Hossein Omidian Savarbaghi, Kia Bazargan:
FPGA placement by graph isomorphism (abstract only). 284 - Xun Chen, Jianwen Zhu:
Regular fabric for regular FPGA (abstract only). 284 - Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai:
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). 284 - Ravikesh Chandra, Oliver Sinnen:
Towards automated optimisation of tool-generated HW/SW sopc designs (abstract only). 285 - Trung Hieu Bui, Tuan Duy Anh Nguyen, Ngoc Thinh Tran:
BBFEX: a bloom-bloomier filter extension for long patterns in FPGA-based pattern matching system (abstract only). 285
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