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Justin S. J. Wong
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- affiliation: Imperial College London. UK
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2020 – today
- 2022
- [j8]Maolin Wang
, Kelvin C. M. Lee
Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network. IEEE Trans. Neural Networks Learn. Syst. 33(7): 2853-2866 (2022)
2010 – 2019
- 2019
- [j7]Runbin Shi
High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing. J. Imaging 5(3): 34 (2019) - [j6]Runbin Shi
A Real-Time Coprime Line Scan Super-Resolution System for Ultra-Fast Microscopy. IEEE Trans. Biomed. Circuits Syst. 13(4): 781-792 (2019) - 2017
- [c14]Justin S. J. Wong
Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory. FPT 2017: 56-63 - 2014
- [j5]Zhenyu Guan, Justin S. J. Wong
Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. IEICE Electron. Express 11(3): 20130912 (2014) - [j4]Zhenyu Guan, Justin S. J. Wong
Mitigation of process variation effect in FPGAs with partial rerouting method. IEICE Electron. Express 11(3): 20140011 (2014) - 2013
- [j3]Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong
Variation and Reliability in FPGAs. IEEE Des. Test 30(6): 50-59 (2013) - [j2]Justin S. J. Wong
Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2307-2320 (2013) - [c13]Zhenyu Guan, Justin S. J. Wong
A variation-adaptive retiming method exploiting reconfigurability. FPL 2013: 1-4 - [c12]Zhenyu Guan, Justin S. J. Wong
Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. FPT 2013: 254-261 - 2012
- [c11]Zhenyu Guan, Justin S. J. Wong
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL 2012: 519-522 - 2011
- [c10]Justin S. J. Wong
Improved delay measurement method in FPGA based on transition probability. FPGA 2011: 163-172 - [c9]Sumanta Chaudhuri
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. FPT 2011: 1-8 - 2010
- [c8]Edward A. Stott, Justin S. J. Wong
Degradation in FPGAs: measurement and modelling. FPGA 2010: 229-238 - [c7]Edward A. Stott, Justin S. J. Wong
Degradation Analysis and Mitigation in FPGAs. FPL 2010: 428-433
2000 – 2009
- 2009
- [j1]Justin S. J. Wong
Self-Measurement of Combinatorial Circuit Delays in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 10:1-10:22 (2009) - 2008
- [c6]N. Pete Sedcole, Justin S. J. Wong
Measuring and modeling FPGA clock variability. FPGA 2008: 258 - [c5]Justin S. J. Wong
Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL 2008: 703-704 - [c4]Justin S. J. Wong
A transition probability based delay measurement method for arbitrary circuits on FPGAs. FPT 2008: 105-112 - [c3]N. Pete Sedcole, Justin S. J. Wong
Modelling and compensating for clock skew variability in FPGAs. FPT 2008: 217-224 - [c2]N. Pete Sedcole, Justin S. J. Wong
Characterisation of FPGA Clock Variability. ISVLSI 2008: 322-328 - 2007
- [c1]Justin S. J. Wong
Self-characterization of Combinatorial Circuit Delays in FPGAs. FPT 2007: 17-23
Coauthor Index
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