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FPGA-based fine-grain parallel computing (abstract only)

Authors:

Andrew W. Hill,

Andrea Di Blas,

Richard HugheyAuthors Info & Claims

FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

Page 283

https://doi.org/10.1145/1950413.1950480

Published: 27 February 2011 Publication History

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Abstract

FPGAs are increasing in computing power at a significant rate while the non-recurring engineering costs and time-to-market remain significant lower than those for application-specific integrated circuits (ASICs), encouraging FPGAs to be used in areas previous dominated by ASICs. In this study, we examine the appropriateness of FPGAs for high-performance, low-volume prodution parallel computing by mapping an existing ASIC-based massively parallel single-instruction, multiple data (SIMD) computer, the UCSC Kestrel, to a variety of FPGAs. The design has a raw peak performance of over 187 billion 8-bit operations per second (OPS), 48 times faster than the original ASIC-based Kestrel, using a Xilinx Virtex-6, and a cost efficiency of up to 81 MOPS/$ using a Xilinx Spartan-3. We also show that we can implement the entire original Kestrel (512 processing elements) as a system on a single programmable chip.

References

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A. Di Blas, D. M. Dahle, M. Diekhans, L. Grate, J. D. Hirschberg, K. Karplus, H. Keller, M. Kendrick, F. J. Mesa-Martinez, D. Pease, E. Rice, A. Schultz, D. Speck, and R. Hughey, "The UCSC Kestrel parallel processor," IEEE Trans Parallel and Distributed Sys, vol. 16, pp. 80--92, January 2005.

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R. Hughey and A. Di Blas, "Finding the next computational model: Experience with the UCSC Kestrel," J Signal Processing Sys, vol. 53, pp. 171--186. October 2007.

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Cited By

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Sandhu FSelamat HAlavi SBehtaji Siahkal Mahalleh V(2017)FPGA-Based Implementation of Kalman Filter for Real-Time Estimation of Tire Velocity and AccelerationIEEE Sensors Journal10.1109/JSEN.2017.272652917:17(5749-5758)Online publication date: 1-Sep-2017
https://doi.org/10.1109/JSEN.2017.2726529

Index Terms

FPGA-based fine-grain parallel computing (abstract only)
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Single instruction, multiple data
2. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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Information

Published In

FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

February 2011

300 pages

ISBN:9781450305549

DOI:10.1145/1950413

General Chair:
John Wawrzynek
University of California, Berkeley, USA
,
Program Chair:
Katherine Compton
University of Wisconsin-Madison, USA

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 February 2011

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FPGA '11

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SIGDA

FPGA '11: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2011

CA, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Sandhu FSelamat HAlavi SBehtaji Siahkal Mahalleh V(2017)FPGA-Based Implementation of Kalman Filter for Real-Time Estimation of Tire Velocity and AccelerationIEEE Sensors Journal10.1109/JSEN.2017.272652917:17(5749-5758)Online publication date: 1-Sep-2017
https://doi.org/10.1109/JSEN.2017.2726529

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Recommendations

Outline of the Ultra Fine Grained Parallel Processing by FPGA

A hardware-efficient computing engine for FPGA-based deep convolutional neural network accelerator

A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers*This work was supported in part by the US Department of Energy under grant DE-FG02-03CH11171.