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Stephen Neuendorffer
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- affiliation: Xilinx, USA
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2020 – today
- 2024
- [j11]Jinming Zhuang
, Jason Lau
CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture. ACM Trans. Reconfigurable Technol. Syst. 17(3): 51:1-51:31 (2024) - [c16]Maksim Levental
An End-to-End Programming Model for AI Engine Architectures. HEART 2024: 135-136 - [i6]Yuyang Rong, Zhanghan Yu, Zhenkai Weng, Stephen Neuendorffer, Hao Chen:
IRFuzzer: Specialized Fuzzing for LLVM Backend Code Generation. CoRR abs/2402.05256 (2024) - 2023
- [j10]Yun Liang, Wei Zhang
Special Issue: "AI Acceleration on FPGAs". ACM Trans. Embed. Comput. Syst. 22(6): 89:1-89:3 (2023) - [c15]Jinming Zhuang
CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture. FPGA 2023: 153-164 - [c14]Tan Nguyen, Zachary Blair, Stephen Neuendorffer, John Wawrzynek:
SPADES: A Productive Design Flow for Versal Programmable Logic. FPL 2023: 65-71 - [i5]Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones
CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture. CoRR abs/2301.02359 (2023) - 2022
- [j9]Ken Eguro
Introduction to Special Issue on FPGAs in Data Centers. ACM Trans. Reconfigurable Technol. Syst. 15(2): 11:1-11:2 (2022) - [j8]Ken Eguro
Introduction to Special Issue on FPGAs in Data Centers, Part II. ACM Trans. Reconfigurable Technol. Syst. 15(3): 22:1-22:2 (2022) - [j7]Jason Cong
FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Trans. Reconfigurable Technol. Syst. 15(4): 51:1-51:42 (2022) - [c13]Hanchen Ye
ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations: invited. DAC 2022: 1355-1358 - [c12]Zhijing Li, Yuwei Ye, Stephen Neuendorffer, Adrian Sampson
Compiler-Driven Simulation of Reconfigurable Hardware Accelerators. HPCA 2022: 619-632 - [c11]Hanchen Ye
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation. HPCA 2022: 741-755 - [i4]Zhijing Li, Yuwei Ye, Stephen Neuendorffer, Adrian Sampson:
Compiler-Driven Simulation of Reconfigurable Hardware Accelerators. CoRR abs/2202.00739 (2022) - 2021
- [i3]Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen:
ScaleHLS: Scalable High-Level Synthesis through MLIR. CoRR abs/2107.11673 (2021) - 2020
- [c10]Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss, Kees A. Vissers, Vivek Sarkar
Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. HPEC 2020: 1-10 - [e2]Stephen Neuendorffer, Lesley Shannon:
FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA, February 23-25, 2020. ACM 2020, ISBN 978-1-4503-7099-8 [contents] - [i2]Prasanth Chatarasi, Stephen Neuendorffer, Samuel Bayliss, Kees A. Vissers, Vivek Sarkar:
Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. CoRR abs/2006.01331 (2020)
2010 – 2019
- 2019
- [e1]Kia Bazargan, Stephen Neuendorffer:
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2019, Seaside, CA, USA, February 24-26, 2019. ACM 2019, ISBN 978-1-4503-6137-8 [contents] - 2018
- [i1]Ryan Kastner, Janarbek Matai, Stephen Neuendorffer:
Parallel Programming for FPGAs. CoRR abs/1805.03648 (2018) - 2013
- [c9]Stephen Neuendorffer, Fernando Martinez-Vallina:
Building zynq® accelerators with Vivado® high level synthesis. FPGA 2013: 1-2 - 2011
- [j6]Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang
High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 473-491 (2011) - [c8]Kees A. Vissers, Stephen Neuendorffer, Juanjo Noguera:
Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools. DATE 2011: 848-850 - [c7]Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis:
High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only). FPGA 2011: 278
2000 – 2009
- 2009
- [j5]Edward A. Lee
Classes and inheritance in actor-oriented design. ACM Trans. Embed. Comput. Syst. 8(4): 29:1-29:26 (2009) - [c6]Kristof Denolf, Stephen Neuendorffer, Kees A. Vissers:
Using C-to-gates to program streaming image processing kernels efficiently on FPGAs. FPL 2009: 626-630 - 2008
- [c5]Stephen Neuendorffer, Kees A. Vissers:
Streaming Systems in FPGAs. SAMOS 2008: 147-156 - 2007
- [j4]Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer:
FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 254-265 (2007) - 2006
- [c4]Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer:
Combining module selection and resource sharing for efficient FPGA pipeline synthesis. FPGA 2006: 179-188 - 2004
- [c3]Edward A. Lee, Stephen Neuendorffer:
Classes and subclasses in actor-oriented design. MEMOCODE 2004: 161-168 - [c2]Stephen Neuendorffer, Edward A. Lee:
Hierarchical reconfiguration of dataflow models. MEMOCODE 2004: 179-188 - [c1]Stephen Neuendorffer:
Modeling Real-World Control Systems: Beyond Hybrid Systems. WSC 2004: 240-248 - 2003
- [j3]Edward A. Lee
Actor-Oriented Design of Embedded Hardware and Software Systems. J. Circuits Syst. Comput. 12(3): 231-260 (2003) - [j2]Johan Eker, Jörn W. Janneck, Edward A. Lee
Taming heterogeneity - the Ptolemy approach. Proc. IEEE 91(1): 127-144 (2003) - 2002
- [j1]Jozsef Ludvig, James G. McCarthy, Stephen Neuendorffer, Sonia R. Sachs:
Reprogrammable Platforms for High-Speed Data Acquisition. Des. Autom. Embed. Syst. 7(4): 341-364 (2002)
Coauthor Index
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