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48th ESSDERC 2018: Dresden, Germany
- 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, September 3-6, 2018. IEEE 2018, ISBN 978-1-5386-5401-9
- Udo Gomez:
Smart Connected Sensors - Enablers for the IoT. 1 - Gary L. Patton:
Unleashing Technology Solutions for a New Era of Connected Intelligence. 2 - Baher Haroun:
Autonomous Vehicles SEnsor Needs. 3 - Evangelos Eleftheriou:
"In-memory Computing": Accelerating AI Applications. 4-5 - Shinichi Takagi, Kimihiko Kato
, Wu-Kang Kim, Kwangwon Jo, Ryo Matsumura
MOS Device Technology using Alternative Channel Materials for Low Power Logic LSI. 6-11 - Louis Hutin, Benoit Bertrand, Romain Maurand, Alessandro Crippa
Si MOS technology for spin-based quantum computing. 12-17 - Luca Sayadi, Giuseppe Iannaccone, Sebastien Sicre, Simone Lavanga, Gianluca Fiori, Oliver Haeberlen, Gilberto Curatola:
Charge Injection in Normally-Off p-GaN Gate AlGaN/GaN-on-Si HFETs. 18-21 - Lars Heuken, Muhammad Alshahed, Alessandro Ottaviani, Mohammed Alomari, Joachim N. Burghartz, Ulrike Waizmann, Thomas Reindl:
Localization and analysis of surface charges trapped in AlGaN/GaN HEMTs using multiple secondary MIS gates. 22-25 - Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai:
Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately. 26-29 - Faiz Arith
High Mobility 4H-SiC MOSFET Using a Thin SiO2/Al2O3 Gate Stack. 30-33 - Kantawong Vuttivorakulchai, Mathieu Luisier, Andreas Schenk:
Effect of Electron-phonon Scattering on the Thermal Conductivity of Si Nanowires. 34-37 - Maeng-Eun Lee, Ulrik Grønbjerg Vej-Hansen, Petr A. Khomyakov, Daniele Stradi, Jess Wellendorff, Søren Smidstrup, Kurt Stokbro:
First-principles study of electron transport through phase-engineered Au - Mo Te2contacts. 38-41 - Jean Choukroun, Marco Pala
High performance WTe2-MoS2in-plane heterojunction Tunnel Field Effect Transistors. 42-45 - Kazuki Maeda, Shinpei Matsuda, Ken Takeuchi, Ryutaro Yasuhara:
Observation and Analysis of Bit-by-Bit Cell Current Variation During Data-Retention of TaOx-based ReRAM. 46-49 - Francesco Maria Puglisi
Energy-Efficient Logic-in-Memory I-bit Full Adder Enabled by a Physics-Based RRAM Compact Model. 50-53 - Jianguo Yang, Xing Li, Tao Wang, Xiaoyong Xue, Zhiliang Hong, Yuanyuan Wang, David Wei Zhang, Hongliang Lu:
A Physically Unclonable Function with BER < 0.35% for Secure Chip Authentication Using Write Speed Variation of RRAM. 54-57 - John R. Jameson, John Dinh, Nathan Gonzales, Shane C. Hollmer, Sue Hsu, David Kim, Foroozan Koushan, Derric Lewis, Ed Runnion, Jeffrey Shields, Aaron Tysdal, Daniel Wang, Venkatesh Gopinath:
Towards Automotive Grade Embedded RRAM. 58-61 - Jonas Doevenspeck, Robin Degraeve, Stefan Cosemans, Philippe Roussel, Bram-Ernst Verhoef, Rudy Lauwereins, Wim Dehaene:
Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications. 62-65 - Ana Lebanov, Andrea Fantini, Robin Degraeve, Manoj Nag, Myriam Willegems, Steve Smout, Soeren Steudel, Jan Genoe
Monolithically integrated 1 TFT-1RRAM non-volatile memory cells fabricated on PI flexible substrate. 66-69 - Michaël Charbonneau, D. Locatelli, S. Lombard, Christophe Serbutoviez
A Large-Area Gravure Printed Process for P-type Organic Thin-Film Transistors on Plastic Substrates. 70-73 - Kyunghwa Lee, Hassan El Dirani, Pascal Fonteneau, Maryline Bawedin, Shingo Sato, Sorin Cristoloveanu:
Sharp switching, hysteresis-free characteristics of Z2-FET for fast logic applications. 74-77 - Mingcheng Chang, Nigel Chan, Vivek Joshi, Sandra Hecker, Udo Ziller, Petra Poth, Alban Zaka, Tom Herrmann, Seunghwan Seo, Hongsik Yoon, Xin Zou, Zhen Xu, Hema Ramamurthy, Torsten Klick, Gabriele Congedo, Youmean Lee, Elke Erben, Gerd Zschaetzsch, Juergen Faul, Jon Kluth, Joerg Schmid, Ralf Van Bentum, Chad Weintraub:
Novel Back Gate Doping Ultra Low Retention Power 22nm FDSOl SRAM for IOT Application. 78-81 - Tulio Chaves de Albuquerque, Françis Calmon
Integration of SPAD in 28nm FDSOI CMOS technology. 82-85 - Umanath Kamath, Tao Yu, Wei Yao, Edward Cullen, John Jennings, Susan Wu, Peng Lim, Brendan Farley, Robert Bogdan Staszewski
BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET. 86-89 - Uwe Vogel, Philipp Wartenberg, Bernd Richter, Stephan Brenner, Karsten Fehse
OLED-on-Silicon Microdisplays: Technology, Devices, Applications. 90-93 - Manuel Moreno-García, Hesong Xu, Leonardo Gasparini
Low-Noise Single Photon Avalanche Diodes in a 110nm CIS Technology. 94-97 - Júlio C. Costa, Arash Pouryazdan, Julianna Panidi
Low Temperature and Radiation Stability of Flexible IGZO TFTs and their Suitability for Space Applications. 98-101 - Indranil Bose, Nagarajan Palavesam
Low Profile Open MEMS and ASIC Packages manufactured by Flexible Hybrid Integration in a Roll-to-Roll compatible process. 102-106 - Daniel Schall:
Integrated Graphene Photonic Devices: Status and Challenges. 107-109 - Paolo Paletti
Electric Double Layer Esaki Tunnel Junction in a 40-nm-Length, WSe2 Channel Grown by Molecular Beam Epitaxy on Al203. 110-113 - Nicolo Oliva, Emanuele A. Casu, Matteo Cavalleri
Double gate n-type WSe2 FETs with high-k top gate dielectric and enhanced electrostatic control. 114-117 - Takamasa Kawanago, Tomoaki Oba, Ryo Ikoma, Hiroyuki Takagi, Shunri Oda:
Gated Four-Probe Method to Evaluate the Impact of SAM Gate Dielectric on Mobility in MoS2 FET. 118-121 - Jens Anders
Towards IC-based quantum sensing - recent achievements and future research trends. 122-125 - Richard C. Jaeger, Jeffrey C. Suhling:
First and Second Order Piezoresistive Characteristics of CMOS FETs: Weak through Strong Inversion. 126-129 - Clemens Mart
CMOS Compatible Pyroelectric Applications Enabled by Doped HfO2 Films on Deep-Trench Structures. 130-133 - Flavien Cozette, Marie Lesecq, Nicolas Defrance, Michel Rousseau, Jean-Claude de Jaeger, Adrien Cutivet, Hassan Maher:
Temperature monitoring of short-gate length AlGaN/GaN HEMT via an integrated sensor. 134-137 - Masumi Saitoh, Shosuke Fujii, Minoru Oda, Marina Yamaguchi, Shoichi Kabuyanagi, Yoko Yoshimura, Kensuke Ota, Kiwamu Sakuma, Yuuichi Kamimuta:
Emerging Non-Volatile Memory and Thin-Film Transistor Technologies for Future 3D-LSI. 138-141 - Benjamin Max
Ferroelectric Tunnel Junctions based on Ferroelectric-Dielectric Hf0.5Zr0.5.O2/ A12O3Capacitor Stacks. 142-145 - Simon Van Beek, Philippe Roussel, Barry J. O'Sullivan, Robin Degraeve, Stefan Cosemans, Dimitri Linten, Gouri Sankar Kar:
Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit. 146-149 - Shun Suzuki, Yoshiaki Deguchi
Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x. 150-153 - David L. Harame:
RF FDSOI Technology and modelling. 154 - Andreia Cathelin:
FD-SOI integration solutions for analog, RF and Millimeter-wave applications. 155 - Edith Beigné:
FDSOI circuit design for high energy efficiency: Wide operating range and ULP applications - a 7-year experience. 156 - Marian Verhelst:
Exploiting FDSOI towards minimum energy point operation in processors and machine learning accelerators. 157 - Bertrand Parvais
Scaling CMOS beyond Si FinFET: an analog/RF perspective. 158-161 - Clarissa Convertino, Cezar B. Zota, Daniele Caimi, Marilyne Sousa, L. Czornomaz:
InGaAs FinFETs 3D Sequentially Integrated on FDSOI Si CMOS with Record Perfomance. 162-165 - Theano A. Karatsori, K. Bennamane, Christoforos G. Theodorou
Static and Low Frequency Noise Characterization of InGaAs MOSFETs and FinFETs on Insulator. 166-169 - Laurence W. Nagel, Colin C. McAndrew:
Why SPICE Is Just As Good And Just As Bad For IC Design As It Was 40 Years Ago. 170-173 - Ayrat Galisultanov, Yann Perrin
Compact MEMS modeling to design full adder in Capacitive Adiabatic Logic. 174-177 - Jens Warmuth, Kay-Uwe Giering
Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh En§ironments. 178-181 - Borivoje Nikolic
Energy-Efficient Design in FDSOI. 182 - Sorin P. Voinigescu:
mmWand high speed solutions enabled by FD-SOI. 183 - Vadim Issakov:
Circuit Design Challenges of Highly-Integrated mm-Wave Radar-Based Sensors in SOI based Technologies. 184 - Anirban Bandyopadhyay:
FD-SOI enabled mmWave telecommunication applications and system architectures. 185 - Erik Bury, Ben Kaczer, Simon Van Beek, Dimitri Linten:
Experimental extraction of BEOL composite equivalent thermal conductivities for application in self-heating simulations. 186-189 - Jinglin Shi, A. Sidelnicov, Kok Wai J. Chew, Mei See Chin, C. Schippel, J. M. M. dos Santos, Frank Schlaphof, Lutz Meinshausen, John R. Long, David L. Harame:
Evolution and Optimization of BEOL MOM Capacitors Across Advanced CMOS Nodes. 190-193 - Marko Simicic
ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology. 194-197 - Raphael Clerc
Device modeling of solution-processed organic solar cells, photodiodes and photo-resistances Invited paper. 198-201 - Zlatan Stanojevic, Georg Strof, Franz Schanovsky, Klaus Steiner, Oskar Baumgartner
Cell Designer - a Comprehensive TCAD-Based Framework for DTCO of Standard Logic Cells. 202-205 - Reinhard Herzer:
Gate Driver Solutions for Modern Power Devices and Topologies. 206-214 - Giulio Ricotti, Valeria Bottarel:
HV Floating Switch Matrix with Parachute Safety Driving for 3D Echography Systems. 215-217 - Katja Puschkarsky
Fast acquisition of activation energy maps using temperature ramps for lifetime modeling of BTI. 218-221 - Stefania Carapezzi
3D TCAD modeling of NO2CNT FET sensors. 222-225 - Thierno-Moussa Bah, Stanjen Didenko, Stéphane Monfray, Thomas Skotnicki
Performance Evaluation of Silicon Based Thermoelectric Generators Interest of Coupling Low Thermal Conductivity Thin Films and a Planar Architecture. 226-229 - Alessandro S. Spinelli, Christian Monzio Compagnoni, Andrea L. Lacaita
Random Dopant Fluctuation and Random Telegraph Noise in Nanowire and Macaroni MOSFETs. 230-233 - Mitiko Miura-Mattausch, Hideyuki Kikuchihara, Tahahiro Kajiwara, Yuta Tanimoto, Atsushi Saito, Takahiro Iizuka
Compact Modeling for Power Efficient Circuit Design. 234-237 - Nikolaos Makris
A Compact Model for Static and Dynamic Operation of Symmetric Double-Gate Junction FETs. 238-241 - Krishna Pradeep, Theano A. Karatsori, Thierry Poiroux, Andre Juge, Patrick Scheer, Gilles Gouget, Emmanuel Josse, Gérard Ghibaudo
Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs. 242-245 - Pascal Alexander 't Hart, Jeroen P. G. van Dijk, Masoud Babaie, Edoardo Charbon, Andrei Vladimirescu, Fabio Sebastiano
Characterization and Model Validation of Mismatch in Nanometer CMOS at Cryogenic Temperatures. 246-249 - Franco Stellari
Novel IC Sub-Threshold IDDQ Signature And Its Relationship To Aging During High Voltage Stress. 250-253 - Luca Pirro, Olaf Zimmerhackl, Alban Zaka, Lars Müller-Meskamp, Ranjith Nelluri, Tom Hermann, Ignasi Cortes-Mayol, Andreas Huschka, Michael Otto, E. Nowak, Anurag Mittal, Jan Hoentschel:
RTN and LFN Noise Performance in Advanced FDSOI Technology. 254-257 - Qitao Hu, Xi Chen, Hans Norström, Shuangshuang Zeng, Yifei Liu
Current gain and low-frequency noise of symmetric lateral bipolar junction transistors on SOI. 258-261
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