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Stefan Cosemans
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2020 – today
- 2024
- [c37]Pascal Alexander Hager, Bert Moons, Stefan Cosemans, Ioannis A. Papistas, Bram Rooseleer, Jeroen Van Loon, Roel Uytterhoeven, Florian Zaruba, Spyridoula Koumousi, Milos Stanisavljevic, Stefan Mach, Sebastiaan Mutsaards, Riduan Khaddam Aljameh, Gua Hao Khov, Brecht Machiels, Cristian Olar, Anastasios Psarras, Sander Geursen, Jeroen Vermeeren, Yi Lu, Abhishek Maringanti, Deepak Ameta, Leonidas Katselas, Noah Hütter, Manuel Schmuck, Swetha Sivadas, Karishma Sharma, Manuel Oliveira, Ramon Aerne, Nitish Sharma, Timir Soni, Beatrice Bussolino, Djordje Pesut, Michele Pallaro, Andrei Podlesnii, Alexios Lyrakis, Yannick Ruffiner, Martino Dazzi, Johannes Thiele, Koen Goetschalckx, Nazareno Bruschi, Jonas Doevenspeck, Bram Verhoef, Stefan Linz, Giuseppe Garcea, Jonathan Ferguson, Ioannis Koltsidas, Evangelos Eleftheriou:
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge. ISSCC 2024: 212-214 - [c36]Farrukh Yasin, A. Palomino, A. Kumar, Valerio Pica, Simon Van Beek, Giacomo Talmelli, V. D. Nguyen, Stefan Cosemans, D. Crotti, Kurt Wostyn, Gouri Sankar Kar, Sebastien Couet:
Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c35]Mohit Gupta, Stefan Cosemans, Peter Debacker, Wim Dehaene:
A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W. ESSCIRC 2023: 417-420 - [c34]Subhali Subhechha, Stefan Cosemans, Attilio Belmonte, Nouredine Rassoul, Shamin Houshmand Sharifi, Peter Debacker, Diederik Verkest, Romain Delhougne, Gouri Sankar Kar:
Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays. IMW 2023: 1-4 - [c33]Swatilekha Majumdar, Stefan Cosemans, Arindam Mallik, Peter Debacker, Francky Catthoor, Jan Van Houdt:
Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator. ISCAS 2023: 1-5 - 2022
- [j10]Hongwu Jiang
, Wantong Li
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators. IEEE Des. Test 39(2): 48-55 (2022) - [j9]Nathan Laubeuf
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. ACM Trans. Design Autom. Electr. Syst. 27(5): 46:1-46:21 (2022) - [c32]Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda
DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. ISSCC 2022: 1-3 - 2021
- [c31]Ioannis A. Papistas, Stefan Cosemans, Bram Rooseleer, Jonas Doevenspeck, Myung Hee Na, Arindam Mallik, Peter Debacker
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration. CICC 2021: 1-2 - [c30]Sidharth Rao
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. IMW 2021: 1-4 - [c29]Simon Van Beek, Siddharth Rao
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. IRPS 2021: 1-5 - [c28]Debjyoti Bhattacharjee
Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration. ISCAS 2021: 1-5 - [c27]Michele Caselli
Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing. NEWCAS 2021: 1-4 - 2020
- [c26]Daniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
Mitigation of Sense Amplifier Degradation Using Skewed Design. DATE 2020: 1614-1617 - [c25]Daniël Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
eSRAM Reliability: Why is it still not optimally solved? DTIS 2020: 1-6
2010 – 2019
- 2019
- [j8]Daniel Kraak
Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1308-1321 (2019) - [c24]Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
Methodology for Application-Dependent Degradation Analysis of Memory Timing. DATE 2019: 162-167 - [c23]Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
Hardware-Based Aging Mitigation Scheme for Memory Address Decoder. ETS 2019: 1-6 - [i1]Bram-Ernst Verhoef, Nathan Laubeuf, Stefan Cosemans, Peter Debacker, Ioannis A. Papistas, Arindam Mallik, Diederik Verkest:
FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference. CoRR abs/1912.09356 (2019) - 2018
- [j7]Innocent Agbo
Impact and mitigation of SRAM read path aging. Microelectron. Reliab. 87: 158-167 (2018) - [c22]Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
Degradation analysis of high performance 14nm FinFET SRAM. DATE 2018: 201-206 - [c21]Jonas Doevenspeck, Robin Degraeve, Stefan Cosemans, Philippe Roussel, Bram-Ernst Verhoef, Rudy Lauwereins, Wim Dehaene:
Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications. ESSDERC 2018: 62-65 - [c20]Simon Van Beek, Philippe Roussel, Barry J. O'Sullivan, Robin Degraeve, Stefan Cosemans, Dimitri Linten, Gouri Sankar Kar:
Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit. ESSDERC 2018: 146-149 - 2017
- [j6]Daniel Kraak
Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3464-3472 (2017) - [c19]Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene:
Mitigation of sense amplifier degradation using input switching. DATE 2017: 858-863 - [c18]Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Dmitry Yakimets, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene:
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. ESSDERC 2017: 256-259 - [c17]Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene:
Dedicated technology threshold voltage tuning for 6T SRAM beyond N7. ICICDT 2017: 1-4 - 2016
- [c16]Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor:
Comparative BTI analysis for various sense amplifier designs. DDECS 2016: 68-73 - [c15]Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene:
Read path degradation analysis in SRAM. ETS 2016: 1-2 - [c14]Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor, Wim Dehaene:
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability. ISVLSI 2016: 725-730 - 2015
- [c13]Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Stefan Cosemans, Pieter Weckx, Praveen Raghavan, Francky Catthoor:
Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier. DTIS 2015: 1-6 - [c12]Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
BTI analysis of SRAM write driver. IDT 2015: 100-105 - [c11]Azam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrián Cristal
NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs. NANOARCH 2015: 51-56 - [c10]Raf Appeltans, Stefan Cosemans, Praveen Raghavan, Diederik Verkest, Liesbet Van der Perre
STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance. NVMSA 2015: 1-6 - 2012
- [j5]Bram Rooseleer, Stefan Cosemans, Wim Dehaene:
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link. IEEE J. Solid State Circuits 47(7): 1784-1796 (2012) - [j4]Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken
Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors. IEEE Micro 32(5): 10-24 (2012) - [c9]Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken
Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM. DATE 2012: 1042-1047 - [c8]Leqi Zhang, Stefan Cosemans, Dirk J. Wouters, Guido Groeseneken
Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write. ESSDERC 2012: 282-285 - 2011
- [j3]Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken
A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy. IEEE J. Solid State Circuits 46(10): 2416-2430 (2011) - [c7]Bram Rooseleer, Stefan Cosemans, Wim Dehaene:
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link. ESSCIRC 2011: 519-522 - [c6]Anselme Vignon, Stefan Cosemans, Wim Dehaene:
A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh. ESSCIRC 2011: 523-526 - [c5]Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken
8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes. ESSCIRC 2011: 531-534 - 2010
- [c4]Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken
A 4.4pJ/access 80MHz, 2K word } 64b memory with write masking feature and variability resilient multi-sized sense amplifier redundancy for wireless sensor nodes applications. ESSCIRC 2010: 358-361
2000 – 2009
- 2009
- [j2]Stefan Cosemans, Wim Dehaene, Francky Catthoor:
A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers. IEEE J. Solid State Circuits 44(7): 2065-2077 (2009) - [c3]Anselme Vignon, Stefan Cosemans, Wim Dehaene, Pol Marchal, Marco Facchini:
A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context. DATE 2009: 929-933 - 2008
- [c2]Stefan Cosemans, Wim Dehaene, Francky Catthoor:
A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability. ESSCIRC 2008: 278-281 - 2007
- [j1]Stefan Cosemans, Wim Dehaene, Francky Catthoor:
A Low-Power Embedded SRAM for Wireless Applications. IEEE J. Solid State Circuits 42(7): 1607-1617 (2007) - [c1]Wim Dehaene, Stefan Cosemans, Anselme Vignon, F. Catthoora, Peter Geens:
Embedded SRAM design in deep deep submicron technologies. ESSCIRC 2007: 384-391
Coauthor Index
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last updated on 2024-11-13 23:48 CET by the dblp team
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