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47th ESSCIRC 2021: Grenoble, France
- 47th ESSCIRC 2021 - European Solid State Circuits Conference, ESSCIR 2021, Grenoble, France, September 13-22, 2021. IEEE 2021, ISBN 978-1-6654-3751-6
- Joël Hartmann, Paolo Cappelletti, Nitin Chawla, Franck Arnaud, Andreia Cathelin:
Artificial Intelligence: Why moving it to the Edge? 1-6 - Jean-René Léquepeys, Marc Duranton, Susana Bonnetier, Sandrine Catrou, Richard Fournel, Thomas Ernst
, Laurent Hérault, D. Louis, A. Jerraya, Alexandre Valentian, François Perruchot, Thomas Signamarcheix, Elisa Vianello, Carlo Reita:
Overcoming the Data Deluge Challenges with Greener Electronics. 7-14 - Jan M. Rabaey, Ana Claudia Arias, Rikky Muller:
Architecting the Human Intranet. 15-20 - Carlo Samori, Luca Bertulessi
Digital PLLs: the modern timing reference for radar and communication systems. 21-27 - Maurits Ortmanns:
Wideband and Low-Power Delta-Sigma ADCs: State of the Art, Trends and Implementation Examples. 28-35 - Ali Sheikholeslami:
The Power of Parallelism in Stochastic Search for Global Optimum: Keynote Paper. 36-42 - Suyash Pati Tripathi, Shai Bonen, Claudia Nastase, Sergiu Iordanescu
Compact Modelling of 22nm FDSOI CMOS Semiconductor Quantum Dot Cryogenic I-V Characteristics. 43-46 - Imran Bashir, Dirk Leipold, Mike Asker, Ali Esmailiyan, Elena Blokhina, David Redmond, Panagiotis Giounanlis, Dennis Andrade-Miceli, Robert Bogdan Staszewski:
Bias Generation and Calibration of CMOS Charge Qubits at 3.5 Kelvin in 22-nm FDSOI. 47-50 - Bozhi Yin, Hayk Gevorgyan, Deniz Onural, Anatol Khilo, Milos A. Popovic
Electronic-Photonic Cryogenic Egress Link. 51-54 - Amita Rawat
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. 55-58 - Damiano Marian, David Soriano, Enrique G. Marin, Giuseppe Iannaccone, Gianluca Fiori:
Electric-field controlled spin transport in bilayer CrI3. 59-62 - Benjamin Gys
Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry. 63-66 - Asma Chabane, Mridula Prathapan, Peter Mueller
Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology. 67-70 - Hung-Chi Han
Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing. 71-74 - Peter Deaville
A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area. 75-78 - Wantong Li
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References. 79-82 - Mona Ezzadeen, Atreya Majumdar, Marc Bocquet, Bastien Giraud, Jean-Philippe Noël, François Andrieu, Damien Querlioz, Jean-Michel Portal:
Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. 83-86 - Laura Bégon-Lours, Mattia Halter, Youri Popoff, Zhenming Yu, Donato Francesco Falcone, Bert Jan Offrein:
High-Conductance, Ohmic-like HfZrO4 Ferroelectric Memristor. 87-90 - Panagiotis Bousoulas, Ch. Papakonstantinopoulos, Dimitris Tsoukalas:
Emulating artificial mechanoreceptor functionalities from SiO2-based memristor and PDMS stretchable sensor for artificial skin applications. 91-94 - Ming Ming Wong, S. B. Shrestha, Vishnu P. Nambiar, Aarthy Mani, Yun Kwan Lee, Eng-Kiat Koh, W. Jiang, Kevin Tshun Chuan Chai, Anh-Tuan Do:
A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. 95-98 - Lixuan Zhu, Weiwei Shan, Jiaming Xu, Yicheng Lu:
AAD-KWS: a sub-µW keyword spotting chip with a zero-cost, acoustic activity detector from a 170nW MFCC feature extractor in 28nm CMOS. 99-102 - Sanjeev Tannirkulam Chandrasekaran, Imon Banerjee
7.5nJ/inference CMOS Echo State Network for Coronary Heart Disease prediction. 103-106 - Yu-Tung Liu, ChuKing Kung
A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS. 107-110 - Benoit Larras, Antoine Frappé
A 43pJ per Inference CBNN-based Compute-in-sensor Associative Memory in 28nm FDSOI. 111-114 - Jiyue Yang, Di Wu, Albert Lee, Seyed Armin Razavi, Puneet Gupta
A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM. 115-118 - Xinrui Guo, Xiaoyang Ma
Exploiting FeFET Switching Stochasticity for Low-Power Reconfigurable Physical Unclonable Function. 119-122 - Gicheol Shin, Donguk Seo
A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions. 123-126 - Viveka Konandur Rajanna
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1, 459 TOPS/W in 28nm. 127-130 - Chengshuo Yu, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim:
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC. 131-134 - Cédric Tubert, Pascal Mellot, Yann Desprez, Celine Mas, Arnaud Authié, Laurent Simony, Grégory Bochet, Stephane Drouard, Jeremie Teyssier, Damien Miclo, Jean-Raphael Bezal, Thibault Augey, Franck Hingant, Thomas Bouchet, Blandine Roig, Aurélien Mazard, Raoul Vergara, Gabriel Mugny, Arnaud Tournier, Frédéric Lalanne, François Roy, Boris Rodrigues Goncalves, Matteo Vignetti, Pascal Fonteneau, Vincent Farys, François Agut, Joao Miguel Melo Santos, David Hadden, Kevin Channon, Christopher Townsend, Bruce Rae, Sara Pellegrini:
4.6µm Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera. 135-138 - Markus Dielacher
Advancements in indirect Time of Flight image sensors in front side illuminated CMOS. 139-142 - Mathieu Sicre, Megan Agnew, Christel Buj, Jean Coignus
Dark Count Rate in Single-Photon Avalanche Diodes: Characterization and Modeling study. 143-146 - Rubén Gómez-Merchán
A high-speed low-power sun sensor with solar cells and continuous operation. 147-150 - Gabriele Quarta
A 0.94-µVrms Input Noise Pixel-Level Continuous Time ΣΔ IADC Interface for THz Sensing. 151-154 - Yuyang Li, Yejoong Kim, Eunseong Moon, Yuxin Gao, Jamie Phillips, Inhee Lee:
An Energy Autonomous Light Intensity Sensor for Monarch Butterfly Migration Tracking. 155-158 - Jonas Pelgrims, Kris Myny
A 36V Ultrasonic Driver for Haptic Feedback Using Advanced Charge Recycling Achieving 0.20CV2f Power Consumption. 159-162 - Peng Guo
A Pitch-Matched Analog Front-End with Continuous Time-Gain Compensation for High-Density Ultrasound Transducer Arrays. 163-166 - Peishuo Li, Tom R. Molderez, Marian Verhelst
A 96-channel 40nm CMOS Fully-Integrated Potentiostat for Electrochemical Monitoring. 167-170 - Guowei Chen
A 0.5 mm2 0.31 V/0.39 V 28 nW/144 nW 65 nm CMOS Solar Cell-Powered Biofuel Cell-Input Biosensing System with PIM/PDM LED Driving for Stand-Alone RF-Less Continuous Glucose Monitoring Contact Lens. 171-174 - R. Midahuen, Bernard Previtali, C. Fontelaye, G. Nonglaton, Sylvain Barraud, V. Stambouli:
Wafer-scale fabrication of biologically sensitive Si nanowire FET: from pH sensing to electrical detection of DNA hybridization. 175-178 - Eva Kempf, Pierre Labeye, Philippe Grosse, Frédéric Boeuf, Stéphane Monfray, Paul G. Charette, Régis Orobtchouk:
Design and Fabrication of a Ring-Coupled Mach-Zehnder Interferometer Gyroscope. 179-182 - Teodor Rosca, Fatemeh Qaderi, Adrian Mihai Ionescu:
High Tuning Range Spiking 1R-1T VO2 Voltage-Controlled Oscillator for Integrated RF and Optical Sensing. 183-186 - Jacob Dean
A 4-31GHz Direct-Conversion Receiver Employing Frequency-Translated Feedback. 187-190 - Thomas Tapen, Alyssa B. Apsel:
A Low Power, 3.5-20GHz Tunable LNA with Out-Of-Band Blocker Filtering Based on Compact, Tunable Transmission Line (CTTL) Resonators in 65nm CMOS. 191-194 - Dong Wei, Tianxiang Wu, Shunli Ma, Yong Chen, Junyan Ren:
A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio. 195-198 - Rehman Akbar
A 38.5-to-60.5 GHz LNA with Wideband Combiner Supporting Cartesian Beamforming Architecture. 199-202 - Nimesh Nadishka Miral, Danilo Manstretta, Rinaldo Castello:
A 17 mW 33 dBm IB-OIP3 0.5-1.5 GHz Bandwidth TIA Based on an Inductor-Stabilized OTA. 203-206 - Lucas Moura Santana
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. 207-210 - Ayman Sakr, Mohamed Atef Hassan, Jens Anders:
A 93.1-dB SFDR, 90.3-dB DR, and 1-MS/s CT Incremental Sigma-Delta Modulator Incorporating a Resistive Dual-RTZ FIR DAC. 211-214 - Abhijeet Taralkar, Francesco Conzatti, Piero Malcovati, Andrea Baschirotto:
A Dual-Mode Second-Order Oversampling Analog-to-Digital Converter. 215-218 - Kyung-Chan An, Neelakantan Narasimman, Tony Tae-Hyoung Kim:
A 0.6-to-1.2 V Scaling Friendly Discrete-Time OTA-Free ΔΣ-ADC for IoT Applications. 219-222 - Mauro Leoncini, Alessandro Bertolini, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni:
An 800-mA Time-Based Boost Converter in 0.18µm BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency. 223-226 - Ziyang Luo, Hoi Lee:
A 40.68MHz Active Rectifier with Cycle-Based On/Off-Delay Compensation for Biomedical Implants. 227-230 - Michael Hanhart, Leo Rolff, Léon Weihs, Jan Grobe
An integrated Boost Controller with MPPT for Submodule PV Applications. 231-234 - Yuyang Li, Eunseong Moon, Jamie Phillips, Inhee Lee:
A Stacked-Photovoltaic-Cell Energy Harvester with >81% Indoor Light Harvesting Efficiency for Millimeter-Scale Energy-Autonomous Sensor Nodes. 235-238 - Arslan Riaz, Vaibhav Bansal, Amit Solomon, Wei An, Qijun Liu
Multi-Code Multi-Rate Universal Maximum Likelihood Decoder using GRAND. 239-246 - Oscar Castañeda, Zachariah Boynton, Seyed Hadi Mirfarshbafan, Shimin Huang, Jamie C. Ye, Alyosha C. Molnar, Christoph Studer
A Resolution-Adaptive 8 mm2 9.98 Gb/s 39.7 pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS. 247-250 - Ivan Bukreyev, Ken Ho, Alyssa B. Apsel:
Scalable Digital Synchronizer for Enabling Hardware-Level BLE Mesh Networks under 1 mW. 251-254 - Hikmet Çeliker
Dual-Input Pseudo-CMOS Logic for Digital Applications on Flexible Substrates. 255-258 - Abraham Gonzalez, Jerry Zhao, Ben Korpan, Hasan Genc, Colin Schmidt, John Charles Wright, Ayan Biswas, Alon Amid, Farhana Sheikh
A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET. 259-262 - Thomas Benz, Luca Bertaccini, Florian Zaruba, Fabian Schuiki, Frank K. Gürkaynak, Luca Benini:
A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range. 263-266 - Angelo Garofalo, Gianmarco Ottavi, Alfio Di Mauro, Francesco Conti, Giuseppe Tagliavini, Luca Benini, Davide Rossi:
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. 267-270 - Sylvain Clerc, Kedar Janardan Dhori, Robin M. Wilson, Rohit Goel, Sébastien Marchal, Franck Pourchon, Christian Dutto, Ricardo Gomez Gomez:
Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies. 271-274 - Emilio Calvanese Strinati, Didier Belot, Alexis Falempin, Jean-Baptiste Doré:
Toward 6G: From New Hardware Design to Wireless Semantic and Goal-Oriented Communication Paradigms. 275-282 - Davide Manente
A 22-31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS. 283-286 - Chung-Ching Lin, Chase Puglisi, Erfan Ghaderi, Soumen Mohapatra, Deukhyoun Heo, Subhanshu Gupta
A 4-Element 800MHz-BW 29mW True-Time-Delay Spatial Signal Processor Enabling Fast Beam-Training with Data Communications. 287-290 - Francesco Chicco, Sammy Cerida Rengifo, Erwan Le Roux, Christian C. Enz:
A 60 GHz QDCO with 11 GHz Seamless Tuning for Low-Power FMCW Radars in 22-nm FDSOI. 291-294 - Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx:
A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS. 295-298 - Surajit Kumar Nath, Junghwan Yoo, Jae-Sung Rieh, Daekeun Yoon:
A 253-280 GHz Wide Tuning Range VCO with -3.5 dBm Peak Output Power in 40-nm CMOS. 299-302 - Shuxin Ming
A 19 GHz Circular-Geometry Quad-Core Tail-Filtering Class-F VCO with -115 dBc/Hz Phase Noise at 1 MHz Offset in 65-nm CMOS. 303-306 - Jun Yin, Pui-In Mak
A Periodically Time-Varying Inductor Applied to The Class-D VCO for Phase Noise Improvement. 307-310 - Tzu-Hsien Yang, Chun-Kai Chiu, Yong-Hwa Wen, Ke-Horng Chen
A Pre-Charge Tracking Technique in the 40MHz High-switching 48-to-5V DC-DC Buck Converter with GaN Switches for Reducing Large Self-commutation Loss and Achieving a High Efficiency of 95.4%. 311-314 - Donghee Cho, Hongseok Shin, Hyunwoo Park, Sein Oh, Taeju Lee, Sohmyung Ha
A Load-Current-Regulating OLED Lamp Driver Using a Hybrid Step-Up Converter with 93.21% Efficiency at a High Conversion Ratio of 4.1. 315-318 - Min Kyu Song, Dong Yan, Dongsheng Brian Ma:
A 8.9W/mm2, 95.4%-Efficiency, CP-Length Tracking Switching Supply Modulator for 5G New Radio mmWave PA Arrays. 319-322 - Joo-Mi Cho, Hyo-Jin Park, Hyunji Choi, Esun Baik, Jeeyoung Shin, Sung-Wan Hong:
A 100-MHz 81.2% All-Paths Inductor-Connected Buck-Converter with Balanced Conduction-Losses and Continuous Path-Currents. 323-326 - Heiko Bürkle, Tobias Klotz, Reiner Krapf, Jens Anders:
A 0.1 MHz to 200 MHz high-voltage CMOS transceiver for portable NMR systems with a maximum output current of 2.0 App. 327-330 - Ayman Mohamed
A readout circuit for tunnel magnetoresistive sensors employing an ultra-low-noise current source. 331-334 - Amir Bozorg, Robert Bogdan Staszewski:
A Charge-Rotating IIR Filter with Linear Interpolation and High Stop-Band Rejection. 335-338 - Marcello De Matteis, Andrea Baschirotto, Elia A. Vallicelli
309-µW 40-MHz 20-dB-Gain Analog Filter in 28nm-CMOS. 339-342 - Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy. 343-346 - Xinjian Liu
An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control. 347-350 - Jooeun Bang
A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency. 351-354 - Yi Tan, Hiroki Ishikuro:
A Switched-Capacitor DC-DC Converter with >77.3% Efficiency and 80 ns Active Transient Response in 40 µA - 4 mA Load Current Range. 355-358 - Edi Emanovic, Joseph Shor, Drazen Jurisic:
An Inverter-Based, Ultra-Low Power, Fully Integrated, Switched-Capacitor DC-DC Buck Converter. 359-362 - Nathalie Deltimple, Potereau Manuel, Anthony Ghiotto:
Fully integrated reflector-based analog predistortion for Ku-band Power Amplifiers Linearization. 363-368 - Thomas Bücher, Janusz Grzyb, Philipp Hillger, Holger Rücker, Bernd Heinemann, Ullrich R. Pfeiffer:
A 239-298 GHz Power Amplifier in an Advanced 130 nm SiGe BiCMOS Technology for Communications Applications. 369-372 - Oner Hanay, Renato Negra:
0.33 mm2 13.3 dB gain sub-6 GHz to 28 GHz transformer-coupled low-voltage upconversion mixer for 5G applications. 373-376 - Enis Kobal
A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS. 377-380 - Tetsuya Iizuka, Hao Xu, Asad A. Abidi:
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW. 381-386 - Hanyue Li, Yuting Shen, Haoming Xin, Eugenio Cantatore, Pieter Harpe:
An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping. 387-390 - Qiang Yu, Xiong Zhou, Kefeng Hu, Zijian Huang, Haiwen Chen, Xin Si, Jinda Yang, Qiang Li:
A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS. 391-394 - Huajun Zhang
A -109.1 dB/-98 dB THD/THD+N Chopper Class-D Amplifier with >83.7 dB PSRR Over the Entire Audio Band. 395-398 - Hyo-Jin Park, Joo-Mi Cho, Hyunji Choi, Esun Baik, Jeeyoung Shin, Sung-Wan Hong:
A 18 µA Rail-to-Rail Class-AB Operational Amplifier with a High-Slew Miller Compensation (HSMC) Technique with 240% Settling Time Reduction in 0.18 µm. 399-402 - Denis Djekic, Matthias Häberle, Ayman Mohamed
A 440-kOhm to 150-GOhm Tunable Transimpedance Amplifier based on Multi-Element Pseudo-Resistors. 403-406 - Mohit Dandekar
An a-IGZO TFT based Op-Amp with 57 dB DC-Gain, 311 KHz Unity-gain Freq., 75 deg. Phase Margin and 2.43 mW Power on Flexible Substrate. 407-410 - Hanzhao Yu, Gyusung Park, Chris H. Kim:
Extreme Temperature Characterization of Amplifier Response up to 300 Degrees Celsius Using Integrated Heaters and On-chip Samplers. 411-414 - Sangyeop Lee, Shinsuke Hara, Ruibing Dong, Kyoya Takano
A 272-GHz CMOS Analog BPSK/QPSK Demodulator for IEEE 802.15.3d. 415-418 - Jin Jin, Jianhui Wu, Rinaldo Castello, Danilo Manstretta:
A 400-µW Low-IF IoT Receiver Front-End with Tunable Charge-Sharing Complex Filter. 419-422 - Yilong Dong, Jiamin Li, Longyang Lin, Tao Tang, Jeong Hoan Park, Kian Ann Ng, Miaolin Zhang, Lian Zhang, Joanne Si Ying Tan, Jerald Yoo
Body-Coupled Power Transceiver with Node-Specific Body-Area Powering. 423-426 - Nilan Udayanga, Manuel Monge:
Dual-band Transceiver with Mutually-coupled On-chip Antennas for Implantable/Wearable Devices. 427-430 - Loai G. Salem:
A Self-Adaptive 4th-Order Filter Based on Tunable N-Path Filters. 431-434 - Yan Zhang, Chia-Jen Liang, Christopher Chen, Andrew Liu, Jason Woo, Sudhakar Pamarti
A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS. 435-438 - Dawei Mai, Yann Donnelly, Michael Peter Kennedy, Stefano Tulisi, James Breslin, Patrick Griffin, Michael Connor, Stephen Brookes, Brian Shelly, Michael Keaveney:
Experimental Verification of Wandering Spur Suppression Technique in a 4.9 GHz Fractional-N Frequency Synthesizer. 439-442 - Yue Gong, Jiangbo Chen, Likang Du, Huiyan Gao, Jiabing Liu, Shengjie Wang, Huan Li, Chunyi Song, Zhiwei Xu:
An Ultra-Low Power K band Balanced Frequency Doubler with a Novel Current-reused Structure. 443-446 - Luca Steinweg, Paolo Valerio Testa, Corrado Carta
A 213 GHz 2 dBm Output-Power Frequency Quadrupler with 45 dB Harmonic Suppression in 130 nm SiGe BiCMOS. 447-450 - Alper Karakuzulu, Mohamed Hussein Eissa, Dietmar Kissinger, Andrea Malignaggi:
A Broadband 110-170 GHz Frequency Multiplier by 4 Chain with 8 dBm Output Power in 130 nm BiCMOS. 451-454 - Jean-Philippe Noel, Manuel Pezzin, Jean-Frédéric Christmann, Lorenzo Ciampolini, M. Le Coadou, M. Diallo, Florent Lepin, B. Blampey, Simone Bacles-Min, R. Wacquez, Bastien Giraud:
A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs. 455-458 - Masoud Nouripayam, Joachim Rodrigues, Xiao Luo, Tom Johansson, Babak Mohammadi:
A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI. 459-462 - Hojun Yoon, Wonjoo Jung, Jaewoo Park, Jindo Byun, Hyungmin Jin, Hyunyoon Cho, Youngmin Kim, Baek-Jin Lim, Young-Chul Cho, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Changsik Yoo, Sang-Hyun Lee:
A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. 463-466 - Sammy Cerida Rengifo, Francesco Chicco, Erwan Le Roux, Christian C. Enz:
An Optimized Low-Power Band-Tuning TX for Short-Range FMCW Radar in 22-nm FDSOI CMOS. 467-470 - Anirudh Kankuppe
A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS. 471-474 - Woonghee Lee, Minkyo Shim, Yunhee Lee
0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. 475-478 - Kristof Dens, Joren Vaes
A PAM4 Dielectric Waveguide Link in 28 nm CMOS. 479-482 - Naftali Weiss, Gregory Cooke, Peter Schvan, Pascal Chevalier, Andreia Cathelin, Sorin P. Voinigescu:
200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator. 483-486 - Jian Luan, Danyu Wu, Xuqiang Zheng, Chen Cai, Linzhen Wu, Lei Zhou, Jin Wu, Xinyu Liu:
A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency. 487-490 - Chenming Zhang, Lucien J. Breems, Qilong Liu, Georgi I. Radulov, Muhammed Bolatkale, Shagun Bajoria, Robert Rutten, Arthur H. M. van Roermund:
A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS. 491-494 - Chengyu Huang, Yushen Fu
A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching. 495-498 - Zheng Sun, Dingxin Xu, Junjun Qiu, Zezheng Liu, Yuncheng Zhang
A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration. 499-502 - Chao Lu, Yi Zhao, Jian Bao, Shr-Lung Chen, Jun Liu, Chin-Ming Chien, Leo Huang, Dingding Zhang, Yong Zhou, Jianqiu Chen, Jinqiang Zhao, Pengfei Yue, Yining Li:
A Highly Efficient Combo Transceiver for 802.11b/g/n/ax and BT/BLE in 22nm CMOS. 503-506 - Oner Hanay, Erkan Bayram, Ahmed Hamed, Renato Negra:
FDDAC-based Transmitter with 2 GHz Modulation Bandwidth and 8 Gbit/s Data Rate. 507-510 - Boyi Zheng, Lu Jie, Michael P. Flynn:
TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping. 511-514 - Behzad Razavi:
Low-Power Techniques for Wireline Systems. 515-522 - Euhan Chong, Faisal Ahmed Musa, Ahmed N. Mustafa, Tim Gao, Peter Krotnev, Rashid Soreefan, Qian Xin, Paul Madeira, Davide Tonietto:
A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET. 523-526 - Chen Cai, Xuqiang Zheng, Yong Chen, Danyu Wu, Jian Luan, Lei Zhou, Jin Wu, Xinyu Liu:
A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS. 527-530
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