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Jorge Luis Lagos-Benites
Person information
- affiliation: imec, Leuven, Belgium
- affiliation (2006 - 2011): Polytechnic University of Turin, Italy
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2020 – today
- 2024
- [c19]Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, Sehoon Park, Jorge-Luis Lagos
, Nereo Markulic, Jan Craninckx:
22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. ISSCC 2024: 396-398 - [c18]Jorge Lagos, Pratap Tumkur Renukaswamy, Nereo Markulic, Ewout Martens, Jan Craninckx:
A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS. VLSI Technology and Circuits 2024: 1-2 - [c17]Nereo Markulic, Johan Nguyen, Jorge Luis Lagos-Benites, Ewout Martens, Jan Craninckx:
A 10GS/s Hierarchical Time-Interleaved ADC for RF-Sampling Applications. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j9]Lai Wei
A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4679-4691 (2023) - [c16]Ewout Martens, Nereo Markulic, Jorge Luis Lagos-Benites, Jan Craninckx:
Calibration Techniques for Optimizing Performance of High-Speed ADCs. CICC 2023: 1-8 - [c15]Lucas Moura Santana
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. ESSCIRC 2023: 389-392 - 2022
- [j8]Jorge Lagos
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. IEEE J. Solid State Circuits 57(4): 1112-1124 (2022) - [j7]Zihao Zheng, Lai Wei, Jorge Lagos
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. IEEE J. Solid State Circuits 57(6): 1673-1683 (2022) - [j6]Lucas Moura Santana
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits 57(7): 2068-2077 (2022) - 2021
- [j5]Benjamin P. Hershberg
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. IEEE J. Solid State Circuits 56(4): 1227-1240 (2021) - [j4]Benjamin P. Hershberg
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. IEEE J. Solid State Circuits 56(8): 2360-2374 (2021) - [j3]Benjamin P. Hershberg
Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2813-2826 (2021) - [c14]Lucas Moura Santana
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC 2021: 207-210 - [c13]Jorge Lagos
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. VLSI Circuits 2021: 1-2 - [c12]Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC. VLSI Circuits 2021: 1-2 - 2020
- [c11]Zihao Zheng, Lai Wei, Jorge Lagos
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. ISSCC 2020: 254-256 - [c10]Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j2]Jorge Lagos
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits 54(2): 403-416 (2019) - [j1]Jorge Lagos
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits 54(3): 646-658 (2019) - [c9]Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos
A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC 2019: 58-60 - [c8]Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC 2019: 68-70 - 2018
- [c7]Jorge Lagos
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC 2018: 1-4 - 2016
- [c6]Antonios Nikas, Olivier Leman, Haiyan Zhou, Jorge-Luis Lagos, Bakul Jitendra Vinchhi, Johann Hauer:
A 83dB SNDR low power readout ASIC for piezoresistive nanogauge based gyroscopes. ISCAS 2016: 2238-2241 - 2015
- [c5]Olivier Leman, Antonios Nikas, Haiyan Zhou, Jorge-Luis Lagos, Bakul Jitendra Vinchhi, Johann Hauer, Guillaume Jourdan
A versatile analog front-end for sensors based on piezoresistive silicon nanowire detection. ISCAS 2015: 666-669 - 2012
- [c4]Paolo Bernardi
On-line software-based self-test of the Address Calculation Unit in RISC processors. ETS 2012: 1-6 - 2011
- [c3]Jorge Luis Lagos-Benites
An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems. DFT 2011: 391-398 - [c2]Jorge Luis Lagos-Benites
A Low-Cost Emulation System for Fast Co-verification and Debug. ETS 2011: 212
2000 – 2009
- 2007
- [c1]Jorge Luis Lagos-Benites
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains. DFT 2007: 291-300
Coauthor Index
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