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38th DFT 2023: Juan-Les-Pins, France
- Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio:
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, October 3-5, 2023. IEEE 2023, ISBN 979-8-3503-1500-4 - Toshinori Hosokawa, Kyohei Iizuka, Masayoshi Yoshimura:
An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers. 1-6 - Benjamin W. Mezger
, Douglas A. dos Santos, Luigi Dilillo, Douglas R. Melo:
Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip. 1-6 - Douglas A. dos Santos, André Martins Pio de Mattos, Douglas R. Melo, Luigi Dilillo:
Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments. 1-6 - S. Bouat, Stéphanie Anceau, Laurent Maingault, Jessy Clédière, Luc Salvo, Rémi Tucoulou:
X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuits. 1-6 - Jin-Fu Li:
Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. 1-6 - Kevin Böhmer, Bruno Forlin, Carlo Cazzaniga, Paolo Rech, Gianluca Furano, Nikolaos Alachiotis, Marco Ottavi
Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs. 1-6 - Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari, Dario Passarello:
Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications. 1-6 - Krishnendu Guha, Gouriprasad Bhattacharyya:
A Self Aware Security Approach for Real Time Neural Network Applications from Row Hammer Attacks in Multi FPGA Multi User Environment. 1-4 - Francisco Fuentes, Sergi Alcaide
Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story. 1-4 - Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Farimah Farahmandi:
EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators. 1-6 - Nasr-Eddine Ouldei Tebina
Simulation Methodology for Assessing X-Ray Effects on Digital Circuits. 1-6 - Rahul Chaurasia, Abhinav Reddy Asireddy, Anirban Sengupta:
Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template. 1-6 - Carolina Imianosky, Douglas A. dos Santos, Douglas R. Melo, Felipe Viel, Luigi Dilillo:
Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit. 1-6 - Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio:
Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator. 1-6 - Amalia-Artemis Koufopoulou, Athanasios Papadimitriou, Aggelos Pikrakis, Mihalis Psarakis, David Hély:
On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks. 1-6 - Hasan Al Shaikh, Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman:
QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy. 1-6 - Payam Habiby, Sebastian Huhn, Rolf Drechsler:
RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks. 1-6 - Yu Xie
Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm. 1-4 - Gabriele Gavarini, Annachiara Ruospo, Ernesto Sánchez:
On the resilience of representative and novel data formats in CNNs. 1-6 - Victor M. van Santen, Florian Klemme, Paul R. Genssler, Hussam Amrouch:
Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits. 1-6 - V. Turco, Annachiara Ruospo, Gabriele Gavarini, Ernesto Sánchez, Matteo Sonza Reorda
Uncovering hidden vulnerabilities in CNNs through evolutionary-based Image Test Libraries. 1-6 - Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Dimitrios Garyfallou, Anastasis Vagenas
Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis. 1-6 - Yu-Guang Chen, Ying-Jing Tsai:
Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches. 1-6 - Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai:
A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage. 1-6 - Shruti Dutta, Sai Charan Rachamadugu Chinni, Abhishek Das, Nur A. Touba:
Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder. 1-4 - Alessandro Palumbo
Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. 1-6 - Shih-Hsu Huang, Wei-Che Cheng, Jin-Fu Li:
Hardware Trojans of Computing-In-Memories: Issues and Methods. 1-6 - Zahin Ibnat, Hadi Mardani Kamali, Farimah Farahmandi:
Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis. 1-6 - Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch, Ulf Schlichtmann:
An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators. 1-6 - Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen, Tianming Ni:
SASL-JTAG: A Light-Weight Dependable JTAG. 1-3 - Junchao Chen, Marko S. Andjelkovic, Milos Krstic
A Machine Learning-driven EDAC Method for Space-Application Memory. 1-6 - Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda
Evaluating the Impact of Aging on Path-Delay Self-Test Libraries. 1-7 - Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov:
On-Chip Sensors Data Collection and Analysis for SoC Health Management. 1-6 - Oana Boncalo, Alexandru Amaricai:
Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes. 1-4 - Glenn H. Chapman, Klinsmann J. Coelho Silva Meneses, Linda Wu, Israel Koren, Zahava Koren:
Image Degradation in Time Due to Interacting Hot Pixels. 1-6 - Christos Georgakidis, Dimitris Valiantzas, Stavros Simoglou, Iordanis Lilitsis, Nikolaos Chatzivangelis
Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis. 1-6 - Clément Fanjas, Driss Aboulkassimi, Simon Pontié, Jessy Clédière:
Exploration of System-on-Chip Secure-Boot Vulnerability to Fault-Injection by Side-Channel Analysis. 1-6 - Haralampos-G. Stratigopoulos, Theofilos Spyrou, Spyridon Raptis:
Testing and Reliability of Spiking Neural Networks: A Review of the State-of-the-Art. 1-8 - Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi, Masayuki Arai:
An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information. 1-6 - Alexandra Takou, Pavlos Stoikos, Moysis Moysis, George Floros
An Efficient Security Closure Methodology for EM-based Attacks on Power Grid Structures. 1-4 - Mohammad Hasan Ahmadilivani, Jaan Raik, Masoud Daneshtalab, Alar Kuusik:
Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks. 1-4 - Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa, Masayoshi Yoshimura:
An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing. 1-6 - Govind Rajhans Jadhav, Sonali Shukla, Virendra Singh:
On Attacking Scan-based Logic Locking Schemes. 1-4 - Wesley Grignani
A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression. 1-6 - Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh:
DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture. 1-6 - Alessandro Palumbo
Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses. 1-6
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last updated on 2024-11-22 19:32 CET by the dblp team
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