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Luca Cassano
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2020 – today
- 2024
- [c37]Bruno Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis, Luca Cassano, Marco Ottavi:
Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes. DATE 2024: 1-2 - [c36]Alessandro Veronesi, Alessandro Nazzari, Dario Passarello, Milos Krstic, Michele Favalli, Luca Cassano, Antonio Miele, Davide Bertozzi, Cristiana Bolchini:
Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space. ETS 2024: 1-6 - 2023
- [j21]Cristiana Bolchini
, Luca Cassano
Fast and Accurate Error Simulation for CNNs Against Soft Errors. IEEE Trans. Computers 72(4): 984-997 (2023) - [j20]Christian Pilato
Optimizing the Use of Behavioral Locking for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 462-472 (2023) - [c35]Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari, Dario Passarello:
Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications. DFT 2023: 1-6 - [c34]Alessandro Palumbo
Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. DFT 2023: 1-6 - [c33]Alessandro Palumbo
Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses. DFT 2023: 1-6 - [c32]Pegdwende Romaric Nikiema, Alessandro Palumbo
Towards Dependable RISC-V Cores for Edge Computing Devices. IOLTS 2023: 1-7 - [e3]Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio:
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, October 3-5, 2023. IEEE 2023, ISBN 979-8-3503-1500-4 [contents] - [i3]Cristiana Bolchini, Luca Cassano, Antonio Miele:
Resilience of Deep Learning applications: a systematic survey of analysis and hardening techniques. CoRR abs/2309.16733 (2023) - 2022
- [j19]Luca Cassano
Design of Fault-Tolerant Distributed Cyber-Physical Systems for Smart Environments. IEEE Embed. Syst. Lett. 14(2): 79-82 (2022) - [j18]Alessandro Palumbo, Luca Cassano
Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer. J. Syst. Archit. 128: 102543 (2022) - [j17]Luca Cassano
DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN. J. Syst. Archit. 129: 102592 (2022) - [j16]Cristiana Bolchini
Fault Impact Estimation for Lightweight Fault Detection in Image Filtering. IEEE Trans. Computers 71(2): 282-295 (2022) - [j15]Matteo Biasielli
Approximation-Based Fault Tolerance in Image Processing Applications. IEEE Trans. Emerg. Top. Comput. 10(2): 648-661 (2022) - [j14]Antonio Miele
A Runtime Resource Management and Provisioning Middleware for Fog Computing Infrastructures. ACM Trans. Internet Things 3(3): 17:1-17:29 (2022) - [j13]Kerem Arikan, Alessandro Palumbo
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches. IEEE Trans. Very Large Scale Integr. Syst. 30(7): 938-951 (2022) - [c31]Cristiana Bolchini, Alberto Bosio, Luca Cassano, Bastien Deveautour, Giorgio Di Natale, Antonio Miele, Ian O'Connor, Elena-Ioana Vatajelu:
Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? DDECS 2022: 7-13 - [c30]Luca Cassano, Elia Lazzeri, Nikita Litovchenko, Giorgio Di Natale:
On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors. DDECS 2022: 172-177 - [c29]Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari:
Selective Hardening of CNNs based on Layer Vulnerability Estimation. DFT 2022: 1-6 - [c28]Luca Cassano, Stefano Di Mascio, Alessandro Palumbo
Is RISC-V ready for Space? A Security Perspective. DFT 2022: 1-6 - [e2]Luca Cassano, Sreejit Chakravarty, Alberto Bosio:
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022. IEEE 2022, ISBN 978-1-6654-5938-9 [contents] - [i2]Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Toschi:
Fast and Accurate Error Simulation for CNNs against Soft Errors. CoRR abs/2206.02051 (2022) - 2021
- [c27]Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele:
Usability-based Cross-Layer Reliability Evaluation of Image Processing Applications. DFT 2021: 1-6 - [c26]Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Giuseppe Bianchi, Marco Ottavi
A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses. DFT 2021: 1-6 - [e1]Luigi Dilillo, Luca Cassano, Athanasios Papadimitriou:
36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021. IEEE 2021, ISBN 978-1-6654-1609-2 [contents] - [i1]Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, Ramesh Karri:
On the Optimization of Behavioral Logic Locking for High-Level Synthesis. CoRR abs/2105.09666 (2021) - 2020
- [j12]Giacomo Tanganelli, Luca Cassano, Antonio Miele, Carlo Vallati:
A methodology for the design and deployment of distributed cyber-physical systems for smart environments. Future Gener. Comput. Syst. 109: 420-430 (2020) - [j11]Matteo Biasielli
A Neural Network Based Fault Management Scheme for Reliable Image Processing. IEEE Trans. Computers 69(5): 764-776 (2020) - [c25]Matteo Biasielli, Luca Cassano, Antonio Miele:
An Approximation-based Fault Detection Scheme for Image Processing Applications. DATE 2020: 1331-1334 - [c24]Cristiana Bolchini, Luca Cassano, Antonio Miele, Matteo Biasielli:
Lightweight Fault Detection and Management for Image Restoration. DFT 2020: 1-6 - [c23]Alperen Bolat
A Microprocessor Protection Architecture against Hardware Trojans in Memories. DTIS 2020: 1-6 - [c22]Cristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele:
Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs. IOLTS 2020: 1-6 - [c21]Ana Lasheras, Ramon Canal, Eva Rodríguez
Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis. IOLTS 2020: 1-6
2010 – 2019
- 2019
- [c20]Matteo Biasielli, Cristiana Bolchini, Luca Cassano, Antonio Miele
A Smart Fault Detection Scheme for Reliable Image Processing Applications. DATE 2019: 704-709 - [c19]Ana Lasheras, Ramon Canal, Eva Rodríguez
Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking. DFT 2019: 1-6 - [c18]Cristiana Bolchini, Luca Cassano, Ivan Montalbano, Giampiero Repole, Andrea Zanetti, Giorgio Di Natale:
HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems. IOLTS 2019: 109-114 - 2018
- [j10]Dario Cozzi, Sebastian Korf, Luca Cassano
OLT(RE)2: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems. IEEE Trans. Emerg. Top. Comput. 6(4): 511-523 (2018) - 2017
- [j9]Cristiana Bolchini
A Fully Automated and Configurable Cost-Aware Framework for Adaptive Functional Diagnosis. IEEE Des. Test 34(2): 79-86 (2017) - 2016
- [j8]Marco Avvenuti, Cinzia Bernardeschi, Luca Cassano, Alessio Vecchio:
Adapting the Duty Cycle to Traffic Load in a Preamble Sampling MAC for WSNs: Formal Specification and Performance Evaluation. Ad Hoc Sens. Wirel. Networks 31(1-4): 101-129 (2016) - [j7]Cinzia Bernardeschi
UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs. Integr. 55: 85-97 (2016) - [j6]Cristiana Bolchini, Luca Cassano
A Novel Approach to Incremental Functional Diagnosis for Complex Electronic Boards. IEEE Trans. Computers 65(1): 42-52 (2016) - [c17]Cristiana Bolchini, Luca Cassano, Antonio Miele:
Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis. DATE 2016: 804-809 - 2015
- [j5]Cinzia Bernardeschi
SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies. J. Comput. Sci. Technol. 30(2): 373-390 (2015) - [j4]Cristiana Bolchini
An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 835-848 (2015) - [c16]Cristiana Bolchini
A configurable board-level adaptive incremental diagnosis technique based on decision trees. DFTS 2015: 227-232 - 2014
- [j3]Cinzia Bernardeschi
ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1342-1355 (2014) - [j2]Federico Baronti
Design and Safety Verification of a Distributed Charge Equalizer for Modular Li-Ion Batteries. IEEE Trans. Ind. Informatics 10(2): 1003-1011 (2014) - [c15]Daniel Cesarini, Luca Cassano
Modeling and Simulation of Energy-Aware Adaptive Policies for Automatic Weather Stations. ES4CPS@DATE 2014: 44 - [c14]Domenico G. Sorrenti, Dario Cozzi, Sebastian Korf, Luca Cassano
Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems. DFT 2014: 203-208 - [c13]Cristiana Bolchini
Machine learning-based techniques for incremental functional diagnosis: A comparative analysis. DFT 2014: 246-251 - [c12]Luca Cassano
An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems. DTIS 2014: 1-6 - [c11]Luca Cassano
A novel adaptive fault tolerant flip-flop architecture based on TMR. ETS 2014: 1-2 - [c10]Luca Cassano
Early assessment of SEU sensitivity through untestable fault identification. IOLTS 2014: 186-189 - [c9]Luca Cassano
Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs. ITC 2014: 1-10 - 2013
- [b1]Luca Cassano:
Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs. University of Pisa, Italy, 2013 - [j1]Cinzia Bernardeschi
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs. J. Syst. Archit. 59(10-D): 1243-1254 (2013) - [c8]Cinzia Bernardeschi
Formal approaches to SEU testing in FPGAs. AHS 2013: 209-216 - [c7]Luca Cassano
On-line testing of permanent radiation effects in reconfigurable systems. DATE 2013: 717-720 - [c6]Cinzia Bernardeschi
Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs. ACM Great Lakes Symposium on VLSI 2013: 7-12 - [c5]Federico Baronti
Mitigation of Single Event Upsets in the control logic of a charge equalizer for Li-ion batteries. IECON 2013: 6758-6763 - 2012
- [c4]Cinzia Bernardeschi
Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs. DFT 2012: 115-120 - [c3]Cinzia Bernardeschi
SEU-X: A SEu un-excitability prover for SRAM-FPGAs. IOLTS 2012: 25-30 - 2011
- [c2]Cinzia Bernardeschi
Failure probability of SRAM-FPGA systems with Stochastic Activity Networks. DDECS 2011: 293-296 - [c1]Cinzia Bernardeschi
Failure Probability and Fault Observability of SRAM-FPGA Systems. FPL 2011: 385-388
Coauthor Index
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last updated on 2024-11-11 21:25 CET by the dblp team
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