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CICC 2023: San Antonio, TX, USA
- IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023. IEEE 2023, ISBN 979-8-3503-9948-6
- Xiaohan Zhang, Sensen Li, Taiyun Chi:
A 38GHz Power-Combined Doherty PA Based on an Extended Rat-Race Coupler Achieving 27.5dBm Saturated Power and 15.0% Efficiency at 6dB Back-Off. 1-2 - Dingxin Xu, Yuncheng Zhang, Hongye Huang
, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. 1-2 - Linran Zhao, Yan Gong, Wei Shi, Raymond Stephany, Wen Li, Yaoyao Jia:
A Wireless Implantable Opto-Electro Neural Interface ASIC for Simultaneous Neural Recording and Stimulation. 1-2 - Yao Qin, Xin Ming, Zhiyi Lin, Zhi-Jiu Wu, Chun-wang Zhuang, Jian-Jun Kuang, Peng Luo, Bo Zhang:
A Monolithic GaN Driver and GaN Power Switch with Power-rail Charging Saturation Bootstrap technique achieving gate rising and falling time ratio of 1.28. 1-2 - Aydin Babakhani, Sidharth Thomas, Sam Razavian:
High-Power, Efficient THz Generation in Silicon for Broadband Sensing and Wireless Communication. 1-8 - Yifan Wu, Sifan Zhou, Miao Sun, Tao Xia, Jian Qian, Lei Wang, Shi Shi, Lebei Cui, Chill Wang, Yuan Li, Hengwei Yu, Zhihong Lin, Lei Qiu, Yajie Qin, Min Sun, Rui Bai, Xuefeng Chen, Patrick Yin Chiang, Shenglong Zhuo:
dToF LIDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128x80 SPAD Sensor, and ML-Based Object Detection for Adaptive Beam-Steering. 1-2 - James Lin
A 4 kHz, 25 μg/√Hz, 3-Axis MEMS Accelerometer ASIC Using Beyond-Resonant-Frequency Sensing. 1-2 - Tianqi Lu, Zu-Yao Chang, Junmin Jiang, Kofi A. A. Makinwa, Sijun Du
A 13.56MHz Fully Integrated 91.8% Efficiency Single-Stage Dual-Output Regulating Voltage Doubler for Biomedical Wireless Power Transfer. 1-2 - Jiahao Song
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. 1-2 - Wen Chen, Yiyang Shu, Xun Luo:
A 21.8-41.6GHz Fractional-N Sub-Sampling PLL with Dividerless Unequal-REF-Delay Frequency-Locked Loop Achieving -246.9dB FoMj and -270.3dB FoMj,N. 1-2 - Edward Jongyoon Choi, Injun Choi, Vincent Lukito, Dong-Hwi Choi, Donghyeon Yi, Ik-Joon Chang, Sohmyung Ha, Minkyu Je:
A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation. 1-2 - Yixiong Yang, Ruoyang Liu, Chenhan Wei, Wenxun Wang, Wenyu Sun, Jinshan Yue, Huazhong Yang, Yongpan Liu:
A 28nm 1.07TFLOPS/mm2 Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing. 1-2 - Haoran Pu, Ahmad Reza Danesh
A CMOS BD-BCI Incorporating Stimulation with Dual-Mode Charge Balancing and Time-Domain Pipelined Recording. 1-2 - Yong-Jun Jo
DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC. 1-2 - Haoyang Jia, Yanjie Wang, Anding Zhu:
A 52-67GHz Ultra-Compact Bi-directional Gate-switching Cascode Amplifier with Tri-coil Broadband Matching in 40-nm CMOS. 1-2 - Junsoo Kim, Geonwoo Ko, Ji-Hoon Kim, Changha Lee, Taewoo Kim, Chan-Hyun Youn, Joo-Young Kim:
A 26.55TOPS/W Explainable AI Processor with Dynamic Workload Allocation and Heat Map Compression/Pruning. 1-2 - Haibiao Zuo, Jiacheng Hao, Jianlin Zhong, Xiaojin Zhao:
A 166F2/bit 0.0136%-Native-BER Physically Unclonable Function Based on Gate-Overhang-Shortened Transistor. 1-2 - Piero Malcovati:
Analog Front-End Circuits for MEMS Microphones. 1-8 - Shiwei Zhang
A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS. 1-2 - Zhen Li, Zhiyuan Chen, Man-Kay Law, Sijun Du, Xu Cheng, Xiaoyang Zeng, Jun Han:
A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter. 1-2 - Jusung Lee, Youngwoo Jo, Wonsik Yu, WooSeok Kim, Michael Choi, Sanghune Park, Jongshin Shin:
A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL. 1-2 - Chuan-Tung Lin, Paul Xuanyuanliang Huang, Jonghyun Oh, Dewei Wang, Mingoo Seok:
iMCU: A 102-μJ, 61-ms Digital In-Memory Computingbased Microcontroller Unit for Edge TinyML. 1-2 - Ali Hajimiri:
Wireless Power Transfer at Distance. 1-4 - Jianqiang Jiang, Junyao Tang, Lei Zhao, Chenchang Zhan, Cheng Huang:
SLiMO: A 61.8% Efficiency Single-Link Multiple-Output Isolated DC-DC Converter Using Low-Cost FPC Micro- Transformer with Local Voltage and Global Power Regulation. 1-2 - Hsing-Yen Tsai, Kuo-Lin Zheng, Ke-Horng Chen
A GaN-on-Si Gate Driver with 14.7X Reduction in Tailing Current Loss and 37.0% Reduction of Reverse Conduction Loss. 1-2 - Sining Pan, Ning Pu, Haiyu Wang, Hanjun Jiang, Zhihua Wang, Huaqiang Wu:
A 7.4μJ.ppm2 Resistance Sensor with ±120ppm (3σ) 1-Point-Trimmed Inaccuracy and <4ppm/°C Temperature Drift from -55°C to 125°C. 1-2 - Jeonghyun Lee, Yoonseo Cho, Jintae Kim, Jaehyouk Choi:
A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter. 1-2 - Cai Li, Haochang Zhi
A 608nW Near-Microphone Keyword-Spotting Chip Using Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN in 28nm CMOS. 1-2 - Shotaro Wada, Yoshikazu Furuta, Soya Taniguchi, Masaya Kondo, Shogo Kawahara, Tomohiro Nezuka:
A 3.9kHz bandwidth and 2μV offset current sensor analog front-end with a capacitively coupled amplifier using a dual frequency conversion technique. 1-2 - Injune Yeo
A 92 F2 / bit Physically Unclonable Function Exploiting Channel Charge Injection and Mismatch Accumulation. 1-2 - Bufan Zhu
Transceiver SoC for Wireless Indoor Sensing Data-fusion. 1-2 - Samuele Fusetto, Elisabetta Moisello, H. Petersen, S. Abedinpour, Piero Malcovati, Edoardo Bonizzoni:
An 87.2%-peak efficiency 4.1 W-output power switchedcapacitor 3-level inverting buck-boost dc-dc converter. 1-2 - Pingda Guan
A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS. 1-2 - Yifei Li
A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path. 1-2 - Minju Park, Kyeongho Eom, Han-Sol Lee, Seung-Beom Ku, Hyung-Min Lee
A 9V-Tolerant 71.4%-Efficiency Stacked-Switched-Capacitor Stimulation System with Level-Adaptive Switching Control and Rapid Stimulus-Synchronized Charge Balancing. 1-2 - Xi Chen, Aly Shoukry, Tianyu Jia, Xin Zhang
A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking. 1-2 - Yipeng Wang, Shanshan Xie, Jacob N. Rohan, Meizhi Wang
A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce. 1-2 - Jiacong Ke
A 52-to-73GHz Tri-Coupled Transformer Based Noise Self-Canceling and Gm-Boosting LNA with 3.78dB NF and 22.4dB Gain in 40nm CMOS. 1-2 - Archisman Ghosh, Md. Abdur Rahman, Debayan Das, Santosh Ghosh, Shreyas Sen:
Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits. 1-2 - Kishalay Datta, Prescott H. McLaughlin, Jason T. Stauth
A Fully-Integrated Direct-Conversion Resonant Switched Capacitor Converter with Modular Multi-Winding Current Ballasting. 1-2 - Zhengyu Chen, Dawei Huang, Mingran Wang, Bowen Yang, Jinuk Luke Shin, Changran Hu, Bo Li, Raghu Prabhakar, Gao Deng, Yongning Sheng, Sihua Fu, Lu Yuan, Tian Zhao, Yun Du, Chen Liu, Jun Yang, Viren Shah, Venkat Srinivasan, Sumti Jairath:
AI SoC Design Challenges in the Foundation Model Era. 1-8 - Mustafa Fayez Ali, Indranil Chakraborty, Sakshi Choudhary, Muya Chang, Dong Eun Kim
A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads. 1-2 - Junghyun Yoon, Moon Hyung Jang
A 243μW 97.4dB-DR 50kHz-BW Multi-Rate CT Zoom ADC with Inherent DAC Mismatch Tolerance. 1-2 - Yi Zhong
An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS. 1-2 - Harrison Liew
Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects. 1-6 - Jae-Hyun Chung, Ye-Dam Kim
An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC. 1-2 - Zhixian Deng, Bingzheng Yang, Wen Chen, Jie Zhou, Changxuan Han, Yifan Li, Yiyang Shu, Xun Luo:
An 8-Element 23-40 GHz Continuously Auto Link-Tracking Phased-Array Transceiver with Time Division Modulator Achieving 7μs Tracking Time, 25.3% TX System Efficiency, 800MHz-64QAM Modulation for 5G NR. 1-2 - Ewout Martens, Nereo Markulic, Jorge Luis Lagos-Benites, Jan Craninckx:
Calibration Techniques for Optimizing Performance of High-Speed ADCs. 1-8 - Xuan Ding
A 1.6pJ/b 65Gb/s Si-Dielectric-Waveguide based Multi-Mode Multi-Drop sub-THz Interconnect in 65nm CMOS. 1-2 - Ruiqi Gao, Mingqiang Guo
Weightings in Incremental ADCs: A Tutorial Review. 1-8 - Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers:
A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR. 1-2 - Xiaodong Xu, Beomsoo Park, Marino De Jesus Guzman, Nima Maghari:
Mixed-Order Correlated Dual-loop Sturdy MASH CT ΔΣ Modulator with Distributed Signal Feed-in and VCO based Quantizer. 1-2 - Yugandhar Khodke, Sadhana Shanmugasundaram
AI Processor with Sparsity-adaptive Real-time Dynamic Frequency Modulation for Convolutional Neural Networks and Transformers. 1-2 - Sandeep Reddy Kukunuru, Loai G. Salem
A 96.6%-Efficiency Inductively Assisted Switched- Capacitor DC-DC Converter with 0.5-to-1.5V Output Voltage Range. 1-2 - Fei Gao, Ting-Jung Chang, Ang Li
DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET. 1-2 - Hector A. Gonzalez, Bernhard Vogginger, Chen Liu, Marco Stolba, Florian Kelber, Heiner Bauer, Stefan Hänzsche, Stefan Scholze, Marc Berthel, Tim Rosmeisl, Liyuan Guo, Dennis Walter, Piash Das, Khaleelulla Khan Nazeer
A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power. 1-2 - Zihao Jiao, Hongrui Luo, Jie Zhang, Xiaofei Wang, Liang Chen, Hong Zhang:
An 84dB-SNDR 1-0 Quasi-MASH NS SAR with LSB Repeating and 12-bit Bridge-Crossing Segmented CDAC. 1-2 - Hon-Piu Lam
4C 3-Level Hybrid Buck Converter for 12~48V-to-1V Point-of-Load Applications. 1-2 - Xinlin Geng
A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels. 1-2 - Xiang-Hui Pan, Buhui Rui, Yuefeng Cao
A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT. 1-2 - Sharvil Patil, Raviteja Theertham, Hajime Shibata, Victor Kozlov, Asha Ganesan, Efram Burlingame, Zhao Li, Rama Thakar, Qianqian Zhang, Yue Yin, Aathreya S. Bhat
A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs. 1-2 - Liqun Feng, Woogeun Rhee, Zhihua Wang:
A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter. 1-2 - Cooper Levy, Zhe Xuan, Duanni Huang, Ranjeet Kumar, Jahnavi Sharma, Taehwan Kim, Chaoxuan Ma, Guan-Lin Su, Songtao Liu, Jinyong Kim, Xinru Wu, Ganesh Balamurugan, Haisheng Rong, James E. Jaussi:
A 3D-integrated 8λ × 32 Gbps λ Silicon Photonic Microring-based DWDM Transmitter. 1-2 - David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Chris Baks, John Timmerwilke, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
Low power cryogenic RF ASICs for quantum computing. 1-8 - Antonio Aprile
A 0.06-mm2 Current-Mode Noise-Shaping SAR based Temperature-to-Digital Converter with a 4.9-nJ Energy/Conversion. 1-2 - Chuhui Wang, Dingxuan Zhang, Jianping Guo:
A 0.24mm2 Bridge-less Hybrid SSHI Interface Circuit for Piezoelectric Energy Harvesting with a Wide Load Range and Up to 1620% Power-Extraction Improvement. 1-2 - Jongho Kim, Gyuchan Cho, Jintae Kim:
A 7GHz ERBW 1.1GS/s 6-bit PVT Tolerant Asynchronous CI-SAR with only 8.5fF Input Capacitance. 1-2 - Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong
A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage. 1-2 - Yuxuan Du, Haitao Ge, Zhuo Chen, Kaize Zhou, Zhengguo Shen, Weiwei Shan:
A 28nm All-Digital, 1.92-7.32mV/LSB, 0.5-2GS/s sample rate, 0-latency Voltage Sensor with Dynamic PVT Calibration for Wide-range Adaptive Voltage Scaling. 1-2 - Yijie Li
A 15.5b-ENOB 335mVpp-Linear-Input-Range 4.7GΩ-Input-Impedance Direct-ADC Based Analog Front-End. 1-2 - Yarallah Koolivand, Yasser Rezayean
A 69MHz-Bandwidth 40V/μs-Slew-rate 3nV/√Hz-Noises 4.5μV-Offset Chopper Operational Amplifier. 1-2 - Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman:
Cryogenic CMOS: design considerations for future quantum computing systems. 1-8 - Heejun Lee, Hyunki Han, Hyun-Sik Kim:
A 4-to-42V Input, 95.5% Efficiency, 3.2μA-IQ, DC-DC Buck Converter Featuring a Leakage-Emulated Bootstrap Re-fresher and Anti-Deadlock Self-Bias Supply for Battery-Powered Automotive Uses. 1-2 - Hoyong Seong, Donghyun Youn, Injun Choi, Junghyup Lee, Sohmyung Ha, Minkyu Je:
A 0.9V 2MHz 6.4x-Slope-Boosted Quadrature-Phase Relaxation Oscillator with 164.2dBc/Hz FoM and 62.5ppm Period Jitter in 0.18μm CMOS. 1-2 - Hamid Jafari Sharemi
A 12.2μW Interference Robust Wake-Up Receiver. 1-2 - Kunyang Liu
A 100-Bit-Output Modeling Attack-Resistant SPN Strong PUF with Uniform and High-Randomness Response. 1-2 - Marcus van Ierssel, Fred N. Buhler, David Moore, Jeffrey Fredenburg:
Synchronous Die-to-Die Signaling Using Aeonic Connect. 1-6 - Jiawei Liao, Hesam Ghiasi, Giorgio Cristiano, Taekwang Jang:
A High-Order-Temperature-Compensated 328kHz On Chip RC Timer Using Time-Interleaved Resistors Achieving 1.5pJ/Cycle and 5.86ppm°C. 1-2 - Yoontae Jung, Jimin Koo, Sein Oh, Seunga Park, Ji-Hoon Suh, Donghee Cho, Minkyu Je:
A 56fJ/Conversion-Step 178dB-FoMS Third-Order Hybrid CT-DT Δ∑ Capacitance-to-Digital Converter. 1-2 - Xiangdong Feng, Yuxuan Luo, Tianyi Cai, Yangfan Xuan, Yunshan Zhang, Yili Shen, Changgui Yang, Qijing Xiao
A 72-Channel Resistive-and-Capacitive Sensor Interface Achieving 0.74 μ W/ Channel and 0.038 mm2/ Channel by Noise-Orthogonalizing and Pad-Sharing Techniques. 1-2 - Nij Dorairaj, David Kehlet, Farhana Sheikh
Open-Source AXI4 Adapters for Chiplet Architectures. 1-5 - Eunseok Lee, Muhammad Ibrahim Wasiq Khan, Xibi Chen, Utsav Banerjee, Nathan M. Monroe, Rabia Tugce Yazicigil, Ruonan Han, Anantha P. Chandrakasan:
A 1.54mm2 Wake-Up Receiver Based on THz Carrier Wave and Integrated Cryptographic Authentication. 1-2 - Chengshuo Yu, Junjie Mu, Kevin Tshun-Chuan Chai, Tony T. Kim, Bongjin Kim:
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates. 1-2 - Matias Jara, Behzad Razavi:
A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply. 1-2 - Mengyu Li
A 1.8V 16μA 136.5dB DR PPG/NIRS Recording IC using Noise Shaping Triple Slope Light to Digital Converter. 1-2 - Hao Guo, Taiyun Chi:
An 86.5-105.6GHz LO Generator with Cascaded Implicit Frequency Quintupling and Tripling Achieving -107.7 dBc/Hz Phase Noise and 191. 2dBc/Hz FoM at 1MHz Offset. 1-2 - Dibo Zhang, Kohei Horii, Katsuhiro Hata, Makoto Takamiya:
Digital Gate ICs for Driving and Sensing Power Devices to Achieve Low-Loss, Low-Noise, and Highly Reliable Power Electronic Systems. 1-7 - Dawei Tang
An Ultra-Wideband Amplifier with A Novel Non- Distributed Butterfly Topology Achieving 2-250 GHz Bandwidth and 4.67 THz GBW in 130nm SiGe BiCMOS. 1-2 - Shiyu Su, Qiaochu Zhang
A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. 1-2 - Ting-Jung Chang, Ang Li
CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. 1-2 - Yuhao Shu
CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing. 1-2 - Scott D. Huss, Chris Moscone, Mark Summers, James Vandersand, Kelvin McCollough, Randall Smith:
Short to Medium-Reach Wireline Transceivers Using Single-Ended Signaling, Clock Forwarding, and Spatial Encoding for Die-to-Die Applications. 1-8 - Caiyu Tong, Zihao Fan, Yuan Gao
A Li-ion Battery Input 96.8% Peak Efficiency Single- Inductor Off-Chip-Capacitor-Free 2-Switch LED Driver with Two-Color Mixing Capability. 1-2 - Chang-Un Park
A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration. 1-2 - Xinzi Xu, Yanxing Suo
A 2.67GΩ 454nVrms 14.9μW Dry-Electrode Enabled ECG-on-Chip with Arrhythmia Detection. 1-2 - Aravind Nagulu, L. M. Ranzani, G. J. Riebell, M. V. Gustafsson, Thomas A. Ohki, Harish Krishnaswamy:
Sub-mW/qubit 5.2-7.2GHz 65nm Cryo-CMOS RX for Scalable Quantum Computing Applications. 1-2 - Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, Mingjie Liu, Xing Zhang, Yuan Wang:
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization. 1-2 - Zhicheng Dong
A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply. 1-2 - Yuqi Su, Tony Tae-Hyoung Kim, Bongjin Kim:
A Reconfigurable lsing Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions. 1-2 - Chao Fan
A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS. 1-2 - Derek Chiou:
System Aspects of Deploying FPGAs for Cloud Infrastructure. 1-2 - Lili Chen
A Low-Power 20Gb/s 196GHz BPSK Wireless Transmitter with Energy Efficiency FoM of 0.15pJ/bit/cm. 1-2 - Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang
A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. 1-2 - Yuanzhe Zhao, Minglei Zhang, Pengyu He, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A Double-Mode Sparse Compute-In-Memory Macro with Reconfigurable Single and Dual Layer Computation. 1-2 - Bahareh Hadidian, Farzad Khoeini, S. M. Hossein Naghavi
A 194-238GHz Fully On-Chip Self-Referenced Frequency Stabilized Radiator for High Range Resolution Imaging. 1-2 - Zhishuai Zhang, Zijie Gao, Siyu Huang, Nan Sun, Lu Jie:
A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking. 1-2 - Vasundhara Damodaran, Ziyu Liu, Jae-Sun Seo, Arindam Sanyal:
A 138-TOPS/W Delta-Sigma Modulator-Based Variable- Resolution Activation in-Memory Computing Macro. 1-2 - Saransh Sharma
A Monolithic 3D Magnetic Sensor in 65nm CMOS with rms Noise and 14.8μW Power. 1-2 - Junwei Huang
A 5V-to-0.5V Inductor-First Inductor-on-Ground Switched Capacitor Multi-Path Hybrid DC-DC Converter. 1-2 - Ying Liu, Zhiyuan Chen, Zhixuan Wang
A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology. 1-2 - ZiXuan Xu
An ELDC-Free 2.78mW 20MHz-BW 75.5dB-SNDR 4th- Order CTSDM Facilitated by 2nd-Order CT NS-SAR and AC-Coupled Negative-R. 1-2 - Morteza Tavakoli Taba, S. M. Hossein Naghavi
A Compact CMOS 363 GHz Autodyne FMCW Radar with 57 GHz Bandwidth for Dental Imaging. 1-2 - K. Gaurav Kumar, Gourab Barik, Baibhab Chatterjee
A 65 nm 2.02 mW 50 Mbps Direct Analog to MJPEG Converter for Video Sensor Nodes using low-noise Switched Capacitor MAC-Quantizer with automatic calibration and Sparsity-aware ADC. 1-2 - Haoyu Zhuang, Nan Sun, Yirui Cao
A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA. 1-2 - Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro:
A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration. 1-2 - Baochuang Wang, Yiling Xie, Jianping Guo, Lin Cheng:
A 150nA IQ, 850mA ILOAD, 90% Efficiency over 10μA to 400mA Loading Range. 1-2 - Woosong Jung, Hyojun Kim
A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces. 1-2 - Ruicong Chen, Anantha P. Chandrakasan, Hae-Seung Lee:
Sniff-SAR: A 9.8fJ/c.-s 12b secure ADC with detectiondriven protection against power and EM side-channel attack. 1-2 - Hwankyu Song, Gyuchan Cho, Jintae Kim:
A 7.9-ENOB 1. 5GS/s Common-Mode and Temperature Insensitive Pipelined-SAR ADC with an On-Chip Temperature-Sensor-Based Stage-Gain Compensation. 1-2 - Jonas Pelgrims, Kris Myny
A 44V Driver Array for Ultrasonic Haptic Feedback in Display Compatible Thin-Film Low Temperature Poly-Silicon. 1-2 - Haoyu Zhuang, Nan Sun, Linzhi Tao, Yizhan Li, Oiang Li:
A Fully-Dynamic kT/C-Noise-Canceled SAR ADC with Trimming-Free Dynamic Amplifier. 1-2
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