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Xiyuan Tang
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2020 – today
- 2024
- [j32]Jiahao Song
, Xiyuan Tang
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM. IEEE J. Solid State Circuits 59(3): 842-854 (2024) - [j31]Mingtao Zhan
A 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp. IEEE J. Solid State Circuits 59(7): 2209-2218 (2024) - [j30]Xin Qiao
A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1706-1718 (2024) - [j29]Qingyu Guo, Haoyang Luo, Meng Li, Xiyuan Tang, Yuan Wang:
CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 5235-5248 (2024) - [c61]Haikang Diao, Haoyang Luo, Jiahao Song, Bocheng Xu, Runsheng Wang, Yuan Wang, Xiyuan Tang:
A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. CICC 2024: 1-2 - [c60]Xin Qiao, Jiahao Song, Youming Yang
MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks. CICC 2024: 1-2 - [c59]Zilong Shen, Jiaiun Tang, Haoyang Luo, Zhongyi Wu, Zongnan Wang, Xing Zhang, Xiyuan Tang, Yuan Wang:
A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation. CICC 2024: 1-2 - [c58]Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang:
PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. DAC 2024: 47:1-47:6 - [c57]Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. DAC 2024: 75:1-75:6 - [c56]Haoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios. DATE 2024: 1-6 - [c55]Jiahao Song
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing. ISSCC 2024: 490-492 - [i2]Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. CoRR abs/2404.13062 (2024) - [i1]Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design. CoRR abs/2406.18873 (2024) - 2023
- [j28]Xiangxing Yang
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. IEEE J. Solid State Circuits 58(5): 1450-1461 (2023) - [j27]Xiyuan Tang
A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. IEEE J. Solid State Circuits 58(9): 2564-2574 (2023) - [j26]Jiahao Song
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 1835-1845 (2023) - [j25]Xin Xin
A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2293-2305 (2023) - [c54]Zilong Shen, Xiyuan Tang, Zhongyi Wu, Haoyang Luo, Zongnan Wang, Mingjie Liu, Xing Zhang, Yuan Wang:
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization. CICC 2023: 1-2 - [c53]Jiahao Song
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. CICC 2023: 1-2 - [c52]Yi Zhong
An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS. CICC 2023: 1-2 - [c51]Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility. DATE 2023: 1-6 - [c50]Xiao Han, Xiyuan Tang, Zibo Ma, Xinzi Xu, Yanxing Suo, Qiao Cai, Yang Zhao:
An NS-SAR ADC with Full-bit High-order Mismatch Shaped CDAC. ISCAS 2023: 1-5 - [c49]Yifan He, Haikang Diao, Chen Tang, Wenbin Jia, Xiyuan Tang, Yuan Wang, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. ISSCC 2023: 130-131 - [c48]Zongnan Wang, Lu Jie, Zichen Kong, Mingtao Zhan, Yi Zhong
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. ISSCC 2023: 176-177 - 2022
- [j24]Xiyuan Tang
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 69(6): 2249-2262 (2022) - [j23]Yi Shen
A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 3965-3975 (2022) - [j22]Xin Qiao
A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2977-2981 (2022) - [c47]Xiao Han, Xiyuan Tang, Yanxing Suo, Qiao Cai, Xinzi Xu, Tianwei Wan, Yang Zhao:
A Vector Pair Based DWA Algorithm for Linearity Enhancement of CDACs in the NS-SAR ADC. APCCAS 2022: 1-5 - [c46]Keren Zhu
Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. ASP-DAC 2022: 519-525 - [c45]Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun:
A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM. CICC 2022: 1-2 - [c44]Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun:
A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR. ISSCC 2022: 1-3 - [c43]Mingtao Zhan, Lu Jie, Xiyuan Tang, Nan Sun:
A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp. ISSCC 2022: 164-166 - 2021
- [j21]Hao Chen
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test 38(2): 19-26 (2021) - [j20]Abhishek Mukherjee
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. IEEE J. Solid State Circuits 56(2): 476-487 (2021) - [j19]Chen-Kai Hsu
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping. IEEE J. Solid State Circuits 56(3): 739-749 (2021) - [j18]Jiaxin Liu
A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping. IEEE J. Solid State Circuits 56(11): 3412-3423 (2021) - [j17]Tzu-Han Wang
A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation. IEEE J. Solid State Circuits 56(12): 3668-3680 (2021) - [j16]Jiahao Song
TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3377-3387 (2021) - [c42]Jiahao Song
A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing. A-SSCC 2021: 1-3 - [c41]Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu
MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. CICC 2021: 1-2 - [c40]Xiangxing Yang, Keren Zhu
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. CICC 2021: 1-2 - [c39]Yi Zhong
An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer. CICC 2021: 1-2 - [c38]Hao Chen, Keren Zhu
Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. DAC 2021: 1243-1248 - [c37]Mingjie Liu, Xiyuan Tang, Keren Zhu
OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. ICCAD 2021: 1-9 - [c36]Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun:
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. ISSCC 2021: 170-172 - [c35]Jiaxin Liu, Dengquan Li, Yi Zhong
27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering. ISSCC 2021: 369-371 - [c34]Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun:
A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. ISSCC 2021: 376-378 - 2020
- [j15]Yi Zhong
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. IEEE J. Solid State Circuits 55(2): 356-368 (2020) - [j14]Yanlong Zhang
A Fractional-N PLL With Space-Time Averaging for Quantization Noise Reduction. IEEE J. Solid State Circuits 55(3): 602-614 (2020) - [j13]Wenda Zhao
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure. IEEE J. Solid State Circuits 55(3): 666-679 (2020) - [j12]Yi Shen
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. IEEE J. Solid State Circuits 55(3): 680-692 (2020) - [j11]Xiyuan Tang
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits 55(4): 1011-1022 (2020) - [j10]Xiyuan Tang
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 55(11): 3064-3075 (2020) - [j9]Xiyuan Tang
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits 55(12): 3248-3259 (2020) - [j8]Jiaxin Liu
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation. IEEE J. Solid State Circuits 55(12): 3260-3270 (2020) - [c33]Mingjie Liu, Wuxi Li, Keren Zhu
S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. ASP-DAC 2020: 193-198 - [c32]Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun:
A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC. A-SSCC 2020: 1-4 - [c31]Chen-Kai Hsu, Xiyuan Tang, Wenda Zhao, Rui Xu, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun:
A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping. CICC 2020: 1-4 - [c30]Mingjie Liu, Keren Zhu
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC 2020: 1-6 - [c29]Mingjie Liu, Keren Zhu
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE 2020: 496-501 - [c28]Hao Chen, Keren Zhu
Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. ICCAD 2020: 18:1-18:8 - [c27]Keren Zhu
Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. ICCAD 2020: 133:1-133:9 - [c26]Yuxuan Huang
An Energy-Efficient Flexible Capacitive Pressure Sensing System. ISCAS 2020: 1-5 - [c25]Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Nan Sun:
9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping. ISSCC 2020: 158-160 - [c24]Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun:
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC 2020: 162-164 - [c23]Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun:
16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation. ISSCC 2020: 258-260 - [c22]Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun:
A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW. VLSI Circuits 2020: 1-2 - [c21]Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, Nan Sun:
A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j7]Shaolan Li, Arindam Sanyal, Kyoungtae Lee
Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs. IEICE Trans. Electron. 102-C(7): 509-519 (2019) - [j6]Linxiao Shen
A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits 54(12): 3375-3385 (2019) - [j5]Jiaxin Liu
Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1342-1354 (2019) - [j4]Jeonggoo Song
A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2876-2887 (2019) - [c20]Mohamed Baker Alawieh, Xiyuan Tang, David Z. Pan:
S2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits. ASP-DAC 2019: 268-273 - [c19]Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure. CICC 2019: 1-3 - [c18]Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun:
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. CICC 2019: 1-4 - [c17]Yanlong Zhang
A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction. CICC 2019: 1-4 - [c16]Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan:
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC 2019: 66 - [c15]Biying Xu, Keren Zhu
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD 2019: 1-8 - [c14]Keren Zhu
GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD 2019: 1-8 - [c13]Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun:
A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor. ISSCC 2019: 64-66 - [c12]Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams
A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. ISSCC 2019: 296-297 - [c11]Xiyuan Tang, Begum Kasap
An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. VLSI Circuits 2019: 140- - [c10]Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun:
A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. VLSI Circuits 2019: 144- - 2018
- [c9]Yi Zhong
A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. A-SSCC 2018: 93-94 - 2017
- [j3]Long Chen
A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction. IEEE J. Solid State Circuits 52(5): 1388-1398 (2017) - [j2]Jeonggoo Song
A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration. IEEE J. Solid State Circuits 52(10): 2563-2575 (2017) - [j1]Long Chen, Kareem Ragab, Xiyuan Tang, Jeonggoo Song, Arindam Sanyal, Nan Sun:
A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 64-II(3): 244-248 (2017) - [c8]Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun:
A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator. A-SSCC 2017: 229-232 - [c7]Miguel Gandara, Wenjuan Guo, Xiyuan Tang, Long Chen, Yeonam Yoon, Nan Sun:
A pipelined SAR ADC reusing the comparator as residue amplifier. CICC 2017: 1-4 - [c6]Jeonggoo Song, Xiyuan Tang, Nan Sun:
A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS. CICC 2017: 1-4 - 2016
- [c5]Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun:
A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration. A-SSCC 2016: 73-76 - [c4]Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun:
A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS. ESSCIRC 2016: 413-416 - [c3]Long Chen, Arindam Sanyal, Ji Ma, Xiyuan Tang, Nan Sun:
Comparator common-mode variation effects analysis and its application in SAR ADCs. ISCAS 2016: 2014-2017 - 2015
- [c2]Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun:
A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction. CICC 2015: 1-4 - [c1]Yeonam Yoon, Kyoungtae Lee
A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration. CICC 2015: 1-4
Coauthor Index
[j31] [j28] [j27] [j25] [c52] [j24] [j23] [c46] [c45] [c44] [c43] [j21] [j20] [j19] [j18] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [j15] [j14] [j13] [j12] [j11] [j10] [j9] [j8] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [j7] [j6] [j5] [j4] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [j3] [j2] [j1] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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